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Showing items 21-45 of 81  (4 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2020-10-07T01:23:16Z Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET M.-L. Fan; VITA PI-HO HU; C.-T. Chuang; P. Su; Y.-N. Chen; M.-L. Fan;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; V. P.-H. Hu; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:16Z Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET M.-L. Fan; VITA PI-HO HU; C.-T. Chuang; P. Su; Y.-N. Chen; M.-L. Fan;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; V. P.-H. Hu; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:16Z Design and Analysis of Robust Tunneling FET SRAM C.-T. Chuang; V. P.-H. Hu; P. Su; Y.-N. Chen; M.-L. Fan; Y.-N. Chen;M.-L. Fan;V. P.-H. Hu;P. Su;C.-T. Chuang; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; VITA PI-HO HU; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:16Z Design and Analysis of Robust Tunneling FET SRAM C.-T. Chuang; V. P.-H. Hu; P. Su; Y.-N. Chen; M.-L. Fan; Y.-N. Chen;M.-L. Fan;V. P.-H. Hu;P. Su;C.-T. Chuang; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; VITA PI-HO HU; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:16Z Design and Analysis of Robust Tunneling FET SRAM C.-T. Chuang; V. P.-H. Hu; P. Su; Y.-N. Chen; M.-L. Fan; Y.-N. Chen;M.-L. Fan;V. P.-H. Hu;P. Su;C.-T. Chuang; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; VITA PI-HO HU; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:15Z Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices VITA PI-HO HU; 胡璧合; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; Y.-N. Chen; VITA PI-HO HU; Pin Su; C.-T. Chuang; Y.-N. Chen;M.-L. Fan;V. P.-H. Hu;Pin Su;C.-T. Chuang; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu
臺大學術典藏 2020-10-07T01:23:15Z Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices VITA PI-HO HU; 胡璧合; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; Y.-N. Chen; VITA PI-HO HU; Pin Su; C.-T. Chuang; Y.-N. Chen;M.-L. Fan;V. P.-H. Hu;Pin Su;C.-T. Chuang; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu
臺大學術典藏 2020-10-07T01:23:15Z Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices VITA PI-HO HU; 胡璧合; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; Y.-N. Chen; VITA PI-HO HU; Pin Su; C.-T. Chuang; Y.-N. Chen;M.-L. Fan;V. P.-H. Hu;Pin Su;C.-T. Chuang; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu
臺大學術典藏 2020-10-07T01:23:15Z Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling 胡璧合; VITA PI-HO HU; C.-T. Chuang; M.-L. Fan;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su
臺大學術典藏 2020-10-07T01:23:15Z Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling 胡璧合; VITA PI-HO HU; C.-T. Chuang; M.-L. Fan;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su
臺大學術典藏 2020-10-07T01:23:15Z Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling 胡璧合; VITA PI-HO HU; C.-T. Chuang; M.-L. Fan;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su
臺大學術典藏 2020-10-07T01:23:15Z Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits C.-T. Chuang; Y.-N. Chen; P. Su; V. P.-H. Hu; S.-Y. Yang; M.-L. Fan;S.-Y. Yang;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; S.-Y. Yang; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU; M.-L. Fan; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:15Z Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits C.-T. Chuang; Y.-N. Chen; P. Su; V. P.-H. Hu; S.-Y. Yang; M.-L. Fan;S.-Y. Yang;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; S.-Y. Yang; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU; M.-L. Fan; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:15Z Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits C.-T. Chuang; Y.-N. Chen; P. Su; V. P.-H. Hu; S.-Y. Yang; M.-L. Fan;S.-Y. Yang;V. P.-H. Hu;Y.-N. Chen;P. Su;C.-T. Chuang; M.-L. Fan; S.-Y. Yang; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU; M.-L. Fan; 胡璧合; VITA PI-HO HU
臺大學術典藏 2020-10-07T01:23:14Z Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET VITA PI-HO HU; 胡璧合; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-W. Hsu; VITA PI-HO HU; Pin Su; V. P.-H. Hu; C.-W. Hsu; M.-L. Fan; C.-W. Hsu;M.-L. Fan;V. P.-H. Hu;Pin Su
臺大學術典藏 2020-10-07T01:23:14Z Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET VITA PI-HO HU; 胡璧合; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-W. Hsu; VITA PI-HO HU; Pin Su; V. P.-H. Hu; C.-W. Hsu; M.-L. Fan; C.-W. Hsu;M.-L. Fan;V. P.-H. Hu;Pin Su
臺大學術典藏 2020-10-07T01:23:14Z Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET VITA PI-HO HU; 胡璧合; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-W. Hsu; VITA PI-HO HU; Pin Su; V. P.-H. Hu; C.-W. Hsu; M.-L. Fan; C.-W. Hsu;M.-L. Fan;V. P.-H. Hu;Pin Su
臺大學術典藏 2020-10-07T01:23:14Z Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits VITA PI-HO HU; 胡璧合; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-J. Chen; Y.-N. Chen; VITA PI-HO HU; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-J. Chen; Y.-N. Chen; Y.-N. Chen;C.-J. Chen;M.-L. Fan;V. P.-H. Hu;Pin Su;C.-T. Chuang
臺大學術典藏 2020-10-07T01:23:14Z Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits VITA PI-HO HU; 胡璧合; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-J. Chen; Y.-N. Chen; VITA PI-HO HU; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-J. Chen; Y.-N. Chen; Y.-N. Chen;C.-J. Chen;M.-L. Fan;V. P.-H. Hu;Pin Su;C.-T. Chuang
臺大學術典藏 2020-10-07T01:23:14Z Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits VITA PI-HO HU; 胡璧合; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-J. Chen; Y.-N. Chen; VITA PI-HO HU; C.-T. Chuang; Pin Su; V. P.-H. Hu; M.-L. Fan; C.-J. Chen; Y.-N. Chen; Y.-N. Chen;C.-J. Chen;M.-L. Fan;V. P.-H. Hu;Pin Su;C.-T. Chuang
臺大學術典藏 2020-10-07T01:23:13Z Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications VITA PI-HO HU; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; Vita Pi-Ho Hu; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合
臺大學術典藏 2020-10-07T01:23:13Z Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications VITA PI-HO HU; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; Vita Pi-Ho Hu; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合
臺大學術典藏 2020-10-07T01:23:13Z Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications VITA PI-HO HU; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; Vita Pi-Ho Hu; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU; C.-H. Yu; M.-L. Fan; K.-C. Yu; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合
臺大學術典藏 2020-10-07T01:23:12Z Optimization of III-V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression VITA PI-HO HU; 胡璧合; C.-T. Wang; V. P.-H. Hu; VITA PI-HO HU; C.-T. Wang; V. P.-H. Hu
臺大學術典藏 2020-10-07T01:23:12Z Optimization of III-V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression VITA PI-HO HU; 胡璧合; C.-T. Wang; V. P.-H. Hu; VITA PI-HO HU; C.-T. Wang; V. P.-H. Hu

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