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Institution	Date	Title	Author
國立交通大學	2014-12-12T02:35:14Z	硬體導向之即時FastICA演算法設計與實現	王昭復; Wang,Jo-Fu; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:59:13Z	多功能低成本EEG訊號處理器設計與實現	黃泊硯; Huang, Po-Yen; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:52:58Z	可支援光線追蹤技術之可程式化高能源效率頂點處理器之設計與實現	劉睿峻; Liu, Ruei-Jyun; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:52:01Z	紋理壓縮與快取技術應用於高能源效率繪圖渲染器之設計與實現	卓曉霜; Cho, Hsiao-Shuang; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:52:01Z	以節省記憶體存取為導向之低內建記憶體網路入侵偵測系統設計與實現	張家榮; Chang, Chia-Jung; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:44:03Z	應用於生醫訊號處理之高能源效益可程式化頂點處理	李坤隆; Lee, Kun-Long; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:43:51Z	高能源效率之訊號分離系統設計與實現	吳廸優; Wu, Di-You; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:43:46Z	應用於八通道EEG訊號分離之高能源效益FastICA設計與實現	陳建勳; Chen, Chien-Shiun; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:43:28Z	高能源效率與低查表之基本運算單元設計與實現	董盈里; Tung, Ying-Li; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:34:18Z	高能源效率可重組基本運算單元之設計與實現	張庭維; Chang, Ting-Wei; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:34:15Z	探討模擬駕駛平台上事件相關之腦波動態變化	李昂穎; Lee, Yang-Yin; 范倫達; 林進燈; Van, Lan-Da; Lin, Chin-Teng
國立交通大學	2014-12-12T01:34:14Z	應用於四通道EEG訊號分離之低功耗FastICA設計與實現	邱思翰; Chiou, Sz-Han; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:34:13Z	應用於三維繪圖系統之三角形設定引擎設計與實作	林丞蔚; Lin, Cheng-Wei; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:20:20Z	運用改良式預先排序搜尋達成快速判斷正交分頻多工系統之最佳字元長度	黃吉霈; Huang, Chi-Pei; 范倫達; Van, Lan-Da
國立交通大學	2014-12-12T01:19:24Z	應用於三維繪圖系統之低複雜度切割演算法與高能源效率幾何引擎設計	許籐耀; Sheu, Ten-Yao; 范倫達; Van, Lan-Da
國立交通大學	2014-12-08T15:48:38Z	A Grouped-Iterative Framework for MIMO Detection	Wu, Di-You; Van, Lan-Da
國立交通大學	2014-12-08T15:47:44Z	FPGA Implementation of 4-Channel ICA for On-line EEG Signal Separation	Huang, Wei-Chung; Hung, Shao-Hang; Chung, Jen-Feng; Chang, Meng-Hsiu; Van, Lan-Da; Lin, Chin-Teng
國立交通大學	2014-12-08T15:47:27Z	A New VLSI 2-D Diagonal-Symmetry Filter Architecture Design	Chen, Pei-Yu; Van, Lan-Da; Reddy, Hari C.; Lin, Chin-Teng
國立交通大學	2014-12-08T15:46:15Z	Front-end amplifier of low-noise and tunable BW/Gain for portable biomedical signal acquisition	Huang, Chun-Chieh; Hung, Shao-Hang; Chung, Jen-Feng; Van, Lan-Da; Lin, Chin-Teng
國立交通大學	2014-12-08T15:46:12Z	Anticipatory access pipeline design for phased cache	Hsueh, Chih-Wen; Chung, Jen-Feng; Van, Lan-Da; Lin, Chin-Teng
國立交通大學	2014-12-08T15:41:16Z	Hierarchical Architecture for Network-on-Chip Platform	Lin, Liang-Yu; Lin, Huang-Kai; Wang, Cheng-Yeh; Van, Lan-Da; Jou, Jing-Yang
國立交通大學	2014-12-08T15:37:51Z	Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures	Chen, Pei-Yu; Van, Lan-Da; Khoo, I-Hung; Reddy, Hari C.; Lin, Chin-Teng
國立交通大學	2014-12-08T15:36:28Z	General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry	Khoo, I. -Hung; Reddy, Hari C.; Van, Lan-Da; Lin, Chin-Teng
國立交通大學	2014-12-08T15:27:15Z	A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System	Van, Lan-Da; Sheu, Ten-Yao
國立交通大學	2014-12-08T15:24:50Z	A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application	Lin, Chin-Teng; Yu, Yuan-Chu; Van, Lan-Da
國立交通大學	2014-12-08T15:23:27Z	Low Complexity Subdivision Algorithm to Approximate Phong Shading Using Forward Difference	Sheu, Teng-Yao; Van, Lan-Da; Jung, Tzung-Rung; Lin, Cheng-Wei; Chang, Ting-Wei
國立交通大學	2014-12-08T15:20:29Z	A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications	Lu, Tsung-Che; Van, Lan-Da; Lin, Chi-Sheng; Huang, Chun-Ming
國立交通大學	2014-12-08T15:19:53Z	A New VLSI 2-D Fourfold-Rotational-Symmetry Filter Architecture Design	Chen, Pei-Yu; Van, Lan-Da; Reddy, Hari C.; Lin, Chin-Teng
國立交通大學	2014-12-08T15:13:51Z	Adaptive low-error fixed-width booth multipliers	Song, Min-An; Van, Lan-Da; Kuo, Sy-Yen
國立交通大學	2014-12-08T15:12:02Z	Efficient Detection Algorithms for MIMO Communication Systems	Wu, Di-You; Van, Lan-Da
國立交通大學	2014-12-08T15:11:08Z	Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor	Lin, Chin-Teng; Yu, Yuan-Chu; Van, Lan-Da
國立交通大學	2014-12-08T15:09:30Z	Classification of driver's cognitive responses using nonparametric single-trial EEG analysis	Lin, Chin-Teng; Ko, Li-Wei; Lin, Ken-Li; Kuo, Bor-Chen; Liang, Sheng-Fu; Chung, I-Fang; Van, Lan-Da
國立交通大學	2014-12-08T15:08:34Z	Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers	Tu, Jin-Hao; Van, Lan-Da
國立交通大學	2014-12-08T15:05:45Z	VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design	Van, Lan-Da; Lin, Chin-Teng; Yu, Yuan-Chu
國立交通大學	2014-12-08T15:04:15Z	Design of Multi-Mode Depth Buffer Compression for 3D Graphics System	Jung, Tzung-Rung; Van, Lan-Da; Sheu, Teng-Yao; Lin, Cheng-Wei; Fang, Wai-Chi
國立交通大學	2014-12-08T15:02:18Z	Reconfigurable depth buffer compression design for 3D graphics system	Jung, Tzung-Rung; Van, Lan-Da; Fang, Wai-Chi; Shen, Teng-Yao
國立臺灣大學	2007	Adaptive Low-Error Fixed-Width Booth Multipliers	Song, Min-An; Van, Lan-Da; Kuo, Sy-Yen
國立臺灣大學	2005-06	Hardware-efficient architecture design of wavelet-based adaptive visible watermarking	Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai
臺大學術典藏	2005-06	Hardware-efficient architecture design of wavelet-based adaptive visible watermarking	Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai; Fan, Yu-Cheng; Van, Lan-Da; Huang, Chun-Ming; Tsao, Hen-Wai
國立臺灣大學	2005-05	A framework for the design of error-aware power-efficient fixed-width Booth multipliers	Song, Min-An; Van, Lan-Da; Yang, Chih-Chyau; Chiu, Shih-Chieh; Kuo, Sy-Yen
國立臺灣大學	2004-07	A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers	Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen
臺大學術典藏	2004-07	A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers	Kuo, Sy-Yen; Huang, Ting-Chun; Van, Lan-Da; Song, Min-An; Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen
國立臺灣大學	2003-12	A low-error and area-time efficient fixed-width booth multiplier	Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen
臺大學術典藏	2003-12	A low-error and area-time efficient fixed-width booth multiplier	Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen; Song, Min-An; Van, Lan-Da; Huang, Ting-Chun; Kuo, Sy-Yen
國立臺灣大學	2001-05	A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage	Tang, Chih-Chun; Lu, Wen-Shih; Van, Lan-Da; Feng, Wu-Shiung
國立臺灣大學	2000-12	Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters	Van, Lan-Da; Feng, Wu-Shiung
國立臺灣大學	2000-12	A new 2-D digital filter using a locally broadcast scheme and its cascade form	Van, Lan-Da; Shing, Tenqchen; Chang, Chi-Hong; Feng, Wu-Shiung
國立臺灣大學	2000-05	A new VLSI architecture without global broadcast for 2-D digital filters	Van, Lan-Da; Tang, Chih-Chun; Shing,Tenqchen; Feng, Wu-Shiung
國立臺灣大學	1999-06	Design of a lower-error fixed-width multiplier for speech processing application	Van, Lan-Da; Wang, Shuenn-Shyang; Tenqchen, Shing; Feng, Wu-Shiung; Jeng, Bor-Shenn
國立臺灣大學	1999-03	A tree-systolic array of DLMS adaptive filter	Van, Lan-Da; Tenqchen, Shing; Chang, Chia-Hsun; Feng, Wu-Shiung

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