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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
國立交通大學 2018-08-21T05:56:48Z Variable-Length VLIW Encoding for Code Size Reduction in Embedded Processors Shyu, Ting-Yu; Su, Bo-Yu; Lin, Tay-Jyi; Yeh, Chingwei; Wang, Jinn-Shyan; Chen, Tien-Fu
國立交通大學 2018-08-21T05:56:38Z Low-Cost Low-Power Droop-Voltage-Aware Delay-Fault-Prevention Designs for DVS Caches Chou, Pei-Yuan; Wu, I-Chen; Lin, Jai-Wei; Lin, Xuan-Yu; Chen, Tien-Fu; Lin, Tay-Jyi; Wang, Jinn-Shyan
國立交通大學 2018-08-21T05:53:00Z ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures Wang, Po-Hao; Chien, Yung-Chen; Tsai, Shang-Jen; Lin, Xuan-Yu; Tanjung, Rizal; Lin, Yi-Sian; Syu, Shu-Wei; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu
臺大學術典藏 2018-07-10T09:48:00Z Probing the Interaction between Prostacyclin Synthase and Prostaglandin H(2) Analogues or Inhibitors via a Combination of Resonance Raman Spectroscopy and Molecular Dynamics Simulation Approaches Wang, Lee-Ho; Chou, Pi-Tai; Yu, Ya-Chien; Lan, Yi-Kang; Chao, Wei-Chih; Lu, Jyh-Feng; Wang, Jinn-Shyan; Yang, Hsiao-Ching; Chen, Hsiao-Hui; Lan, Yi-Kang; Yu, Ya-Chien; Chou, Pi-Tai; Wang, Lee-Ho; Chao, Wei-Chih; Lu, Jyh-Feng; Wang, Jinn-Shyan; Yang, Hsiao-Ching; Chen, Hsiao-Hui
國立交通大學 2017-04-21T06:56:40Z Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations Wang, Po-Hao; Cheng, Wei-Chung; Yu, Yung-Hui; Kao, Tang-Chieh; Tsai, Chi-Lun; Chang, Pei-Yao; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu
國立交通大學 2017-04-21T06:56:22Z Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors Wang, Po-Hao; Tsai, Shang-Jen; Tanjung, Rizal; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu
國立交通大學 2016-03-28T00:05:45Z A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS Lin, Tay-Jyi; Chien, Cheng-An; Chang, Pei-Yao; Chen, Ching-Wen; Wang, Po-Hao; Shyu, Ting-Yu; Chou, Chien-Yung; Luo, Shien-Chun; Guo, Jiun-In; Chen, Tien-Fu; Chuang, Gene C. H.; Chu, Yuan-Hua; Cheng, Liang-Chia; Su, Hong-Men; Jou, Chewnpu; Ieong, Meikei; Wu, Cheng-Wen; Wang, Jinn-Shyan
國立交通大學 2015-12-02T03:00:50Z Adaptive Variable-Latency Cache Management for Low-Voltage Caches Yu, Yung-Hui; Wang, Po-Hao; Chen, Tien-Fu; Lin, Tay-Jyi; Wang, Jinn-Shyan
國立交通大學 2014-12-08T15:35:18Z Variation-Aware and Adaptive-Latency Accesses for Reliable Low Voltage Caches Wang, Po-Hao; Cheng, Wei-Chung; Yu, Yung-Hui; Kao, Tang-Chieh; Tsai, Chi-Lun; Chang, Pei-Yao; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu
國立交通大學 2014-12-08T15:22:40Z A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security Cheng, Chieh-Jen; Wang, Chao-Ching; Ku, Wei-Chun; Chen, Tien-Fu; Wang, Jinn-Shyan
國立臺灣大學 2011 Probing the Interaction between Prostacyclin Synthase and Prostaglandin H(2) Analogues or Inhibitors via a Combination of Resonance Raman Spectroscopy and Molecular Dynamics Simulation Approaches Chao, Wei-Chih; Lu, Jyh-Feng; Wang, Jinn-Shyan; Yang, Hsiao-Ching; Chen, Hsiao-Hui; Lan, Yi-Kang; Yu, Ya-Chien; Chou, Pi-Tai; Wang, Lee-Ho
國立臺灣大學 2002 Stopped-flow kinetic study of the peroxidase reactions of mangano-microperoxidase-8 Yeh, Hui-Chun; Yu, Chia-Huei; Wang, Jinn-Shyan; Chen, Shei-Tein; Su, Y. Oliver; Lin, Wann-Yin
國立臺灣大學 2001 Stopped-flow kinetic study of the H2O2 oxidation of substrates catalyzed by microperoxidase-8 Yeh, Hui-Chun; Wang, Jinn-Shyan; Su, Y. Oliver; Lin, Wann-Yin
國立中正大學 2000 VLSI電路設計 王進賢; Wang, Jinn-Shyan
淡江大學 1995-04-30 Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan; Chu, Yuan-hua; Wu, Tain-shun; Wu, Chung-yu
淡江大學 1993-01 Analysis and design of a new race-free four-phase CMOS logic Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan
淡江大學 1992-05 High-speed four-phase CMOS logic for complex high-speed VLSI Wu, Chung-yu; Cheng, Kuo-hsing; Wang, Jinn-shyan

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