|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"wang tahui"
Showing items 1-10 of 122 (13 Page(s) Totally)
1 2 3 4 5 6 7 8 9 10 > >>
View [10|25|50] records per page
| 國立交通大學 |
2020-10-05T02:01:09Z |
Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
|
Chiang, Hung-Li; Chen, Tzu-Chiang; Song, Ming-Yuan; Chen, Yu-Sheng; Chiu, Jung-Piao; Chiang, Katherine; Manfrini, Mauricio; Cai, Jin; Gallagher, William J.; Wang, Tahui; Diaz, Carlos H.; Wong, H. -S. Philip |
| 國立交通大學 |
2020-02-02T23:54:29Z |
Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device
|
Su, Po-Cheng; Jiang, Cheng-Min; Chen, Yu-Jia; Wang, Chih-Chieh; Li, Kai-Shin; Lin, Chao-Cheng; Wang, Tahui |
| 國立交通大學 |
2020-01-02T00:04:18Z |
Investigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on ${V}_{{t}}$ Retention Loss in a Multilevel Charge Trap Flash Memory
|
Liu, Yu-Heng; Zhan, Ting-Chien; Wang, Tahui; Tsai, Wen-Jer; Lu, Tao-Cheng; Chen, Kuang-Chao; Lu, Chih-Yuan |
| 國立交通大學 |
2019-08-02T02:24:17Z |
Investigation of Data Pattern Effects on Nitride Charge Lateral Migration in a Charge Trap Flash Memory by Using a Random Telegraph Signal Method
|
Liu, Y. H.; Lin, H. Y.; Jiang, C. M.; Wang, Tahui; Tsai, W. J.; Lu, T. C.; Chen, K. C.; Lu, Chih-Yuan |
| 國立交通大學 |
2019-08-02T02:24:17Z |
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
|
Lin, T. W.; Ku, S. H.; Cheng, C. H.; Lee, C. W.; Ijen-Huang; Tsai, Wen-Jer; Lu, T. C.; Lu, W. P.; Chen, K. C.; Wang, Tahui; Lu, Chih-Yuan |
| 國立交通大學 |
2019-08-02T02:24:17Z |
Correlation between SET-State Current Level and Read Disturb Failure Time in a Resistive Switching Memory
|
Su, P. C.; Jiang, C. M.; Wang, C. W.; Wang, Tahui |
| 國立交通大學 |
2019-04-02T06:04:53Z |
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
|
Ku, S. H.; Lin, T. W.; Cheng, C. H.; Lee, C. W.; Chen, Ti-Wen; Tsai, Wen-Jer; Lu, T. C.; Lu, W. P.; Chen, K. C.; Wang, Tahui; Lu, Chih-Yuan |
| 國立交通大學 |
2019-04-02T06:04:37Z |
Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
|
Lu, C. C.; Cheng, C. C.; Chiu, H. P.; Lin, W. L.; Chen, T. W.; Ku, S. H.; Tsai, Wen-Jer; Lu, T. C.; Chen, K. C.; Wang, Tahui; Lu, Chih-Yuan |
| 國立交通大學 |
2019-04-02T05:59:54Z |
Modeling of Read-Disturb-Induced SET-State Current Degradation in a Tungsten Oxide Resistive Switching Memory
|
Su, Po-Cheng; Jiang, Cheng-Min; Wang, Chih-Wei; Wang, Tahui |
| 國立交通大學 |
2019-04-02T05:59:51Z |
Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
|
Chou, Y. L.; Chung, Y. T.; Wang, Tahui; Ku, S. H.; Zou, N. K.; Chen, Vincent; Lu, W. P.; Chen, K. C.; Lu, Chih-Yuan |
Showing items 1-10 of 122 (13 Page(s) Totally)
1 2 3 4 5 6 7 8 9 10 > >>
View [10|25|50] records per page
|
