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Showing items 1-3 of 3 (1 Page(s) Totally)
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| 國立交通大學 |
2020-01-02T00:03:29Z |
An 8.8-GS/s 8b Time-Interleaved SAR ADC with 50-dB SFDR Using Complementary Dual-Loop-Assisted Buffers in 28nm CMOS
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Wang, X. Shawn; Chan, Chi-Hang; Du, Jieqiong; Wong, Chien-Heng; Li, Yilei; Du, Yuan; Kuan, Yen-Cheng; Hu, Boyu; Chang, Mau-Chung Frank |
| 國立交通大學 |
2019-12-13T01:09:58Z |
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
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Du, Yuan; Du, Li; Gu, Xuefeng; Du, Jieqiong; Wang, X. Shawn; Hu, Boyu; Jiang, Mingzhe; Chen, Xiaoliang; Iyer, Subramanian S.; Chang, Mau-Chung Frank |
| 國立交通大學 |
2019-04-02T05:59:57Z |
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS
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Wang, X. Shawn; Jin, Xin; Du, Jieqiong; Li, Yilei; Du, Yuan; Wong, Chien-Heng; Kuan, Yen-Cheng; Chan, Chi-Hang; Chang, Mau-Chung Frank |
Showing items 1-3 of 3 (1 Page(s) Totally)
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