| 國立成功大學 |
2022 |
Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size
|
Yu, X.-R.;Chuang, M.-H.;Chang, S.-W.;Chang, W.-H.;Hong, T.-C.;Chiang, Chiang C.-H.;Lu, W.-H.;Yang, C.-Y.;Chen, W.-J.;Lin, J.-H.;Wu, P.-H.;Sun, T.-C.;Kola, S.;Yang, Yang Y.-S.;Da, Y.;Sung, P.-J.;Wu, C.-T.;Cho, T.-C.;Luo, G.-L.;Kao, Kao K.-H.;Chiang, M.-H.;Ma, W.C.-Y.;Su, C.-J.;Chao, T.-S.;Maeda, T.;Samukawa, Samukawa S.;Li, Y.;Lee, Y.-J.;Wu, Wu W.-F.;Tarng, J.-H.;Wang, Y.-H. |
