|
English
|
正體中文
|
简体中文
|
0
|
|
???header.visitor??? :
52778727
???header.onlineuser??? :
601
???header.sponsordeclaration???
|
|
|
|
???tair.name??? >
???browser.page.title.author???
|
"wei kai cheng"???jsp.browse.items-by-author.description???
Showing items 1-9 of 9 (1 Page(s) Totally)
1
View [10|25|50] records per page
| 國立彰化師範大學 |
2011-04 |
A high current efficiency rail-to-rail buffer for low drop-out regulators with load regulation-enhanced
|
Peng, Guang-Yu; Wei, Kai-Cheng |
| 國立彰化師範大學 |
2010-04 |
Using the charge recycling technique for low power PLA design
|
Xiao, C.-T. ; Wei, Kai-Cheng |
| 國立彰化師範大學 |
2008-08 |
An Efficient Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction
|
Lin, Chih-Hung; Wei, Kai-Cheng |
| 國立彰化師範大學 |
2007-06 |
Encoding Bus for Low Power and Coupling Effects Minimization
|
Lin, H. W. ; Wei, Kai-Cheng |
| 國立彰化師範大學 |
2007-03 |
Low Power Bus Encoding Technique Considering Coupling Effects
|
Lin, H. W. ; Wei, Kai-Cheng |
| 國立彰化師範大學 |
1997-01 |
Low Test-Application Time Method for EEPLA testing
|
Wei, Kai-Cheng ; Liu, B. D. ; Tang, J. J. |
| 國立彰化師範大學 |
1994-07 |
An efficient Algorithm for Selecting Bipartite Row and Column Folding of Programmable Logic Arrays
|
Liu, B. D. ; Wei, Kai-Cheng |
| 國立彰化師範大學 |
1994 |
Combining the Folding and Testing for Programmable Logic Arrays
|
Wei, Kai-Cheng; Liu, B. D. |
| 國立彰化師範大學 |
1994 |
Low Overhead Design for Programmable Logic Array with Testability
|
Wei, Kai-Cheng ; Sheu, J. J. ; Liu, B. D. |
Showing items 1-9 of 9 (1 Page(s) Totally)
1
View [10|25|50] records per page
|
