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"wey i chyn"的相关文件
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| 國立臺灣大學 |
2009 |
Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits
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Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu; Chen, Jie |
| 臺大學術典藏 |
2009 |
Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits
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Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu; Chen, Jie; Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu; Chen, Jie |
| 國立臺灣大學 |
2008 |
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits
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Wey, I-Chyn; Chen, You-Gang; Wu, An-Yeu |
| 國立臺灣大學 |
2006-05 |
A portable all-digital pulsewidth control loop for SOC applications
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Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu |
| 國立臺灣大學 |
2006-05 |
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 臺大學術典藏 |
2006-05 |
A portable all-digital pulsewidth control loop for SOC applications
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Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu; Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu |
| 臺大學術典藏 |
2006-05 |
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu; Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2005-07 |
A high speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chen, You-Gang; Wu, Chia-Tsun; Wang, Wei; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A scalable DCO design for portable ADPLL designs
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chang, Lung-Hao; Chen, You-Gang; Chang, Shih-Hung; Wu, An-Yeu |
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