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"wong cheng chi"的相關文件
顯示項目 1-10 / 13 (共2頁)
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| 國立交通大學 |
2019-04-02T06:04:47Z |
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
|
Wong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia |
| 國立交通大學 |
2017-04-21T06:48:17Z |
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
|
Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立交通大學 |
2015-07-21T08:28:03Z |
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder
|
Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-16T06:15:49Z |
APPARATUS OF MULTI-STAGE NETWORK FOR ITERATIVE DECODING AND METHOD THEREOF
|
WONG, Cheng-Chi; LEE, Yung-Yu; LAI, Ming-Wei; LIN, Chien-Ching; CHANG, Hsie-Chia; LEE, Chen-Yi |
| 國立交通大學 |
2014-12-12T01:22:36Z |
運用平行架構及無競爭式交錯器之渦輪碼解碼器
|
翁政吉; Wong, Cheng-Chi; 張錫嘉; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-08T15:41:57Z |
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
|
Wong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-08T15:38:32Z |
A Multiple Code-Rate Turbo Decoder Based on Reciprocal Dual Trellis Architecture
|
Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-08T15:33:16Z |
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver
|
Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-08T15:32:53Z |
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
|
Lin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-08T15:21:54Z |
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
|
Wong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia |
顯示項目 1-10 / 13 (共2頁)
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每頁顯示[10|25|50]項目
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