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Showing items 1-25 of 25 (1 Page(s) Totally)
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| 臺大學術典藏 |
2022-03-16T01:32:14Z |
Voxelwise relationships between distribution volume ratio and cerebral blood flow: Implications for analysis of b-amyloid images
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Sojkova J.; JOSHUA GOH; Bilgel M.; Landman B.; Yang X.; Zhou Y.; An Y.; Beason-Held L.L.; Kraut M.A.; Wong D.F.; Resnick S.M. |
| 臺大學術典藏 |
2020-06-16T06:31:24Z |
Design and analysis of FPGA/FPIC switch modules.
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Chang, Yao-Wen;Wong, D. F.;Wong, C. K.; Chang, Yao-Wen; Wong, D. F.; Wong, C. K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2020-06-16T06:31:23Z |
FPGA global routing based on a new congestion metric.
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Chang, Yao-Wen;Wong, D. F.;Wong, C. K.; Chang, Yao-Wen; Wong, D. F.; Wong, C. K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2020-06-16T06:31:22Z |
Switch module design with application to two-dimensional segmentation design.
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Zhu, Kai;Wong, D. F.;Chang, Yao-Wen; Zhu, Kai; Wong, D. F.; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T15:24:39Z |
Voxelwise relationships between distribution volume ratio and cerebral blood flow: Implications for analysis of b-amyloid images
|
Sojkova, J.;Goh, J.;Bilgel, M.;Landman, B.;Yang, X.;Zhou, Y.;An, Y.;Beason-Held, L.L.;Kraut, M.A.;Wong, D.F.;Resnick, S.M.; JOSHUA GOH |
| 臺大學術典藏 |
2018-09-10T07:03:51Z |
Graph matching-based algorithms for FPGA segmentation design
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YAO-WEN CHANG; Wong, D.F.; Lin, Jai-Ming; Chang, Yao-Wen |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
Timing-driven routing for symmetrical-array-based FPGAs
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Zhu, Kai; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
Graph-theoretic sufficient condition for FPGA/FPIC switch-module routability
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Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
Algorithms for an FPGA switch module routing problem with application to global routing
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Thakur, S.; Chang, Y.-W.; Wong, D.F.; Muthukrishnan, S.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
Universal switch modules for fpga design
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Chang, Y.-W.;Wong, D.F.;Wong, C.K.; Chang, Y.-W.; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
On a new timing-driven routing tree problem
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Chang, Yao-Wen;Wong, D.F.;Zhu, Kai;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Zhu, Kai; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
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Chen, Chung-Ping;Chang, Yao-Wen;Wong, D.F.; Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:31Z |
Design and analysis of FPGA/FPIC switch modules
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Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
FPGA global routing based on a new congestion metric
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Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:45Z |
New global routing algorithm for FPGAs
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Chang, Yao-Wen;Thakur, Shashidhar;Zhu, Kai;Wong, D.F.; Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Analysis of FPGA/FPIC switch modules
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Chang, Y.-W.; Zhu, K.; Wu, G.-M.; Wong, D.F.; Wong, C.K.; Chang, Yao-Wen |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Switch module design with application to two-dimensional segmentation design
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Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Timing-driven routing for symmetrical array-based FPGAs
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Chang, Y.-W.; Zhu, K.; Wong, D.F.; YAO-WEN CHANG |
| 南華大學 |
2003-01 |
Analysis of FPGA/FPIC switch modules
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吳光閔;Wu, Guang-Ming;Chang, Yao-Wen;Zhu, Kai;Wong, D. F.;Wong, C. K. |
| 國立臺灣大學 |
2003 |
Analysis of FPGA/FPIC switch modules
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Chang, Yao-Wen; Zhu, Kai; Wu, Guang-Ming; Wong, D. F.; Wong, C. K. |
| 國立臺灣大學 |
2002 |
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation
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LEE, YU-MIN; CHEN, CHARLIE CHUNG-PING; CHANG, YAO-WEN; WONG, D.F. |
| 國立臺灣大學 |
2002 |
Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes
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Lee, Yu-Min; Chen, Charlie Chung-Ping; Wong, D. F. |
| 臺大學術典藏 |
2002 |
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation
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Lee, Yu-Min; Chen, Charlie Chung-Ping; Chang, Yao-Wen; Wong, D.F.; LEE, YU-MIN; CHEN, CHARLIE CHUNG-PING; CHANG, YAO-WEN; WONG, D.F. |
| 國立臺灣大學 |
2000 |
Timing-driven routing for symmetrical-array-based FPGAs
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CHANG, YAO-WEN; ZHU, KAI; WONG, D. F. |
| 臺大學術典藏 |
1996 |
Universal switch-module design for symmetric-array-based FPGAs
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Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
Showing items 1-25 of 25 (1 Page(s) Totally)
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