|
"wong d f"的相关文件
显示项目 11-25 / 25 (共1页)
1
每页显示[10|25|50]项目
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
On a new timing-driven routing tree problem
|
Chang, Yao-Wen;Wong, D.F.;Zhu, Kai;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Zhu, Kai; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
|
Chen, Chung-Ping;Chang, Yao-Wen;Wong, D.F.; Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:31Z |
Design and analysis of FPGA/FPIC switch modules
|
Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
FPGA global routing based on a new congestion metric
|
Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:45Z |
New global routing algorithm for FPGAs
|
Chang, Yao-Wen;Thakur, Shashidhar;Zhu, Kai;Wong, D.F.; Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Analysis of FPGA/FPIC switch modules
|
Chang, Y.-W.; Zhu, K.; Wu, G.-M.; Wong, D.F.; Wong, C.K.; Chang, Yao-Wen |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Switch module design with application to two-dimensional segmentation design
|
Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Timing-driven routing for symmetrical array-based FPGAs
|
Chang, Y.-W.; Zhu, K.; Wong, D.F.; YAO-WEN CHANG |
| 南華大學 |
2003-01 |
Analysis of FPGA/FPIC switch modules
|
吳光閔;Wu, Guang-Ming;Chang, Yao-Wen;Zhu, Kai;Wong, D. F.;Wong, C. K. |
| 國立臺灣大學 |
2003 |
Analysis of FPGA/FPIC switch modules
|
Chang, Yao-Wen; Zhu, Kai; Wu, Guang-Ming; Wong, D. F.; Wong, C. K. |
| 國立臺灣大學 |
2002 |
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation
|
LEE, YU-MIN; CHEN, CHARLIE CHUNG-PING; CHANG, YAO-WEN; WONG, D.F. |
| 國立臺灣大學 |
2002 |
Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes
|
Lee, Yu-Min; Chen, Charlie Chung-Ping; Wong, D. F. |
| 臺大學術典藏 |
2002 |
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation
|
Lee, Yu-Min; Chen, Charlie Chung-Ping; Chang, Yao-Wen; Wong, D.F.; LEE, YU-MIN; CHEN, CHARLIE CHUNG-PING; CHANG, YAO-WEN; WONG, D.F. |
| 國立臺灣大學 |
2000 |
Timing-driven routing for symmetrical-array-based FPGAs
|
CHANG, YAO-WEN; ZHU, KAI; WONG, D. F. |
| 臺大學術典藏 |
1996 |
Universal switch-module design for symmetric-array-based FPGAs
|
Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
显示项目 11-25 / 25 (共1页)
1
每页显示[10|25|50]项目
|
