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Taiwan Academic Institutional Repository >
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"wong h s philip"
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| 國立交通大學 |
2020-10-05T02:01:30Z |
First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate
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Cheng, Chao-Ching; Chung, Yun-Yan; Li, Ming-Yang; Lin, Chao-Ting; Li, Chi-Feng; Chen, Jyun-Hong; Lai, Tung-Yen; Li, Kai-Shin; Shieh, Jia-Min; Su, Sheng-Kai; Chiang, Hung-Li; Chen, Tzu-Chiang; Li, Lain-Jong; Wong, H-S Philip; Chien, Chao-Hsin |
| 國立交通大學 |
2020-10-05T02:01:09Z |
Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
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Chiang, Hung-Li; Chen, Tzu-Chiang; Song, Ming-Yuan; Chen, Yu-Sheng; Chiu, Jung-Piao; Chiang, Katherine; Manfrini, Mauricio; Cai, Jin; Gallagher, William J.; Wang, Tahui; Diaz, Carlos H.; Wong, H. -S. Philip |
| 國立交通大學 |
2020-03-01 |
Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)
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Li, Lain-Jong; Chang, Wen-Hao; Yakobson, Boris I.; Fu, Qiang; Zhang, Yanfeng; Chueh, Wei-Chen; Chao, Tzu-Ang; Li, Rongtan; Pan, Shuangyuan; Wong, H. -S. Philip; Wen, Chao-Kai; Tseng, Chien-Chih; Chuu, Chih-Piao; Chen, Tse-An |
| 國立交通大學 |
2020-01-02T00:04:18Z |
Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
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Chung, Yun-Yan; Lu, Kuan-Cheng; Cheng, Chao-Ching; Li, Ming-Yang; Lin, Chao-Ting; Li, Chi-Feng; Chen, Jyun-Hong; Lai, Tung-Yen; Li, Kai-Shin; Shieh, Jia-Min; Su, Sheng-Kai; Chiang, Hung-Li; Chen, Tzu-Chiang; Li, Lain-Jong; Wong, H-S Philip; Jian, Wen-Bin; Chien, Chao-Hsin |
| 國立交通大學 |
2019-04-02T06:01:02Z |
Recommended Methods to Study Resistive Switching Devices
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Lanza, Mario; Wong, H-S Philip; Pop, Eric; Ielmini, Daniele; Strukov, Dimitri; Regan, Brian C.; Larcher, Luca; Villena, Marco A.; Yang, J. Joshua; Goux, Ludovic; Belmonte, Attilio; Yang, Yuchao; Puglisi, Francesco M.; Kang, Jinfeng; Magyari-Kope, Blanka; Yalon, Eilam; Kenyon, Anthony; Buckwell, Mark; Mehonic, Adnan; Shluger, Alexander; Li, Haitong; Hou, Tuo-Hung; Hudec, Boris; Akinwande, Deji; Ge, Ruijing; Ambrogio, Stefano; Roldan, Juan B.; Miranda, Enrique; Sune, Jordi; Pey, Kin Leong; Wu, Xing; Raghavan, Nagarajan; Wu, Ernest; Lu, Wei D.; Navarro, Gabriele; Zhang, Weidong; Wu, Huaqiang; Li, Runwei; Holleitner, Alexander; Wurstbauer, Ursula; Lemme, Max C.; Liu, Ming; Long, Shibing; Liu, Qi; Lv, Hangbing; Padovani, Andrea; Pavan, Paolo; Valov, Ilia; Jing, Xu; Han, Tingting; Zhu, Kaichen; Chen, Shaochuan; Hui, Fei; Shi, Yuanyuan |
| 國立交通大學 |
2018-08-21T05:56:59Z |
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
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Chang, Chih-Cheng; Liu, Jen-Chieh; Shen, Yu-Lin; Chou, Teyuh; Chen, Pin-Chun; Wang, I-Ting; Su, Chih-Chun; Wu, Ming-Hong; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Wong, H-S Philip; Hou, Tuo-Hung |
| 國立交通大學 |
2018-08-21T05:56:56Z |
Statistical Study of RRAM MLC SET Variability Induced by Filament Morphology
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Hsu, Chung-Wei; Zheng, Xin; Wu, Yi; Hou, Tuo-Hung; Wong, H. -S. Philip |
| 國立交通大學 |
2018-08-21T05:54:28Z |
AC stress and electronic effects on SET switching of HfO2 RRAM
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Liu, Jen-Chieh; Magyari-Kope, Blanka; Qin, Shengjun; Zheng, Xin; Wong, H. -S. Philip; Hou, Tuo-Hung |
| 國立交通大學 |
2018-08-21T05:53:09Z |
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
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Chen, Hong-Yu; Brivio, Stefano; Chang, Che-Chia; Frascaroli, Jacopo; Hou, Tuo-Hung; Hudec, Boris; Liu, Ming; Lv, Hangbing; Molas, Gabriel; Sohn, Joon; Spiga, Sabina; Teja, V. Mani; Vianello, Elisa; Wong, H. -S. Philip |
| 國立交通大學 |
2017-04-21T06:49:48Z |
Design and Optimization Methodology for 3D RRAM Arrays
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Deng, Yexin; Chen, Hong-Yu; Gao, Bin; Yu, Shimeng; Wu, Shih-Chieh; Zhao, Liang; Chen, Bing; Jiang, Zizhen; Liu, Xiaoyan; Hou, Tuo-Hung; Nishi, Yoshio; Kang, Jinfeng; Wong, H. -S. Philip |
Showing items 1-10 of 14 (2 Page(s) Totally)
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