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"wu a y"
Showing items 101-150 of 196 (4 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T08:15:39Z |
Regional ACO-based routing for load-balancing in NoC systems
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Hsin, H.-K.;Chang, E.-J.;Chao, C.-H.;Wu, A.-Y.; Hsin, H.-K.; Chang, E.-J.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm
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Shen, W.-C.; Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU; Wu, C.-T.;Shen, W.-C.;Wang, W.;Wu, A.-Y.; Wu, C.-T. |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
ACO-based cascaded adaptive routing for traffic balancing in NoC systems
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Chang, E.-J.;Chao, C.-H.;Jheng, K.-Y.;Hsin, H.-K.;Wu, A.-Y.; Chang, E.-J.; Chao, C.-H.; Jheng, K.-Y.; Hsin, H.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
Cost-effective constrained particle filter for indoor localization
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Chao, C.-H.;Chu, C.-Y.;Chao, M.-A.;Wu, A.-Y.; Chao, C.-H.; Chu, C.-Y.; Chao, M.-A.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
Efficient parallelized particle filter design on CUDA
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Chao, M.-A.;Chu, C.-Y.;Chao, C.-H.;Wu, A.-Y.; Chao, M.-A.; Chu, C.-Y.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system
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Chen, Y.-L.;Jheng, T.-J.;Zhan, C.-Z.;Wu, A.-Y.; Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems
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Lin, S.-Y.;Shen, W.-C.;Hsu, C.-C.;Chao, C.-H.;Wu, A.-Y.; Lin, S.-Y.; Shen, W.-C.; Hsu, C.-C.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems
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AN-YEU(ANDY) WU; Wu, A.-Y.; Jheng, T.-J.; Chen, Y.-L.; Jheng, K.-Y.; Zhan, C.-Z.; Zhan, C.-Z.;Jheng, K.-Y.;Chen, Y.-L.;Jheng, T.-J.;Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
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Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; Tsai, T.-H.; AN-YEU(ANDY) WU; Lin, C.-H.;Chen, C.-Y.;Wu, A.-Y.;Tsai, T.-H. |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Multilevel LINC system designs for power efficiency enhancement of transmitters
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Jheng, K.-Y.;Chen, Y.-J.;Wu, A.-Y.; Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
PAC Duo SoC performance analysis with ESL design methodology
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Chuang, I.-Y.;Chang, C.-W.;Fan, T.-Y.;Yeh, J.-C.;Ji, K.-M.;Ma, J.-L.;Wu, A.-Y.;Lin, S.-Y.; Chuang, I.-Y.; Chang, C.-W.; Fan, T.-Y.; Yeh, J.-C.; Ji, K.-M.; Ma, J.-L.; Wu, A.-Y.; Lin, S.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:59Z |
A scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems
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Lin, S.-Y.;Hsu, C.-C.;Wu, A.-Y.; Lin, S.-Y.; Hsu, C.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:59Z |
A triple-mode LDPC decoder design for IEEE 802.11n system
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Chao, M.-A.;Wen, J.-Y.;Shih, X.-Y.;Wu, A.-Y.; Chao, M.-A.; Wen, J.-Y.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:58Z |
A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications
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AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Zhan, C.-Z.; Shih, X.-Y.; Shih, X.-Y.;Zhan, C.-Z.;Lin, C.-H.;Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T07:37:58Z |
A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices
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Shih, X.-Y.;Zhan, C.-Z.;Wu, A.-Y.; Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Algorithm-based low-power transform coding architectures: The multirate approach
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Wu, A.-Y.; Liu, K.J.R.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
System architecture of an adaptive reconfigurable DSP computing engine
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Wu, A.-Y.; Liu, K.J.R.; Raghupathy, A.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Overview of ITRI PAC project - From VLIW DSP processor to multicore computing platform
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AN-YEU(ANDY) WU; Wu, A.-Y.; Chu, Y.-H.; Lin, T.-J.; Liu, C.-N.; Tseng, S.-Y. |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-Balanced IP Mapping Algorithm for 2D-mesh on-chip-networks
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Lin, T.-J.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-balanced routing algorithm for irregular mesh-based on-chip networks
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Lin, S.-Y.; Huang, C.-H.; Chao, C.-H.; Huang, K.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Algorithm-based low-power and high-performance multimedia signal processing
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Liu, K.J.R.; Wu, A.-Y.; Raghupathy, A.; Chen, J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-performance scheduling algorithm for partially parallel LDPC decoder
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Zhan, C.-Z.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-throughput 12-mode CTC decoder for WiMAX standard
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Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-throughput dual-mode single/double binary map processor design for wireless wan
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Chen, C.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
Location-constrained particle filter for rssi-based indoor human positioning and tracking system
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Chao, C.-H.; Chu, N.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
Low-power traceback MAP decoding for double-binary convolutional turbo decoder
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Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
An 8.29 mm2 52 mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 μm CMOS process
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Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation
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Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system
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Chen, Y.-L.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Cost-effective joint echo-NEXT canceller designs for 10GBase-T ethernet systems based on a shortened impulse response filter (SIRF) scheme
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Chen, Y.-L.; Hsu, M.-F.; Lai, J.-T.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits
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Wey, I.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:41Z |
A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications
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AN-YEU(ANDY) WU; Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules
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Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
On the fixed-point properties of mixed-scaling-rotation cordic algorithm
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Yu, C.-L.; Yu, T.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
On the new stopping criteria of iterative turbo decoding by using decoding threshold
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Li, F.-M.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Robust packet detector based automatic gain control algorithm for OFDM-based ultra-wideband systems
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Chu, N.-Y.; Lai, J.-T.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Multilevel LINC system design for power efficiency enhancement
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Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
A power-aware reconfigurable rendering engine design with 453MPixels/s, 16.4MTriangles/s performance
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Chao, C.-H.; Kuo, Y.-L.; Wu, A.-Y.; Chien, W.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
A systematic design approach to the band-tracking packet detector in OFDM-based ultrawideband systems
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Lai, J.-T.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design
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Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
Joint AGC-equalization algorithm and VLSI architecture for wirelined transceiver designs
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Lai, J.-T.; Wu, A.-Y.; Lee, C.-H.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement
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Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system
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Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A clock-fault tolerant architecture and circuit for reliable nanoelectronics system
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Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:22:08Z |
Multilevel LINC system design for wireless transmitters
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Chen, Y.-J.; Jheng, K.-Y.; Wu, A.-Y.; Tsao, H.-W.; Tzeng, B.; HEN-WAI TSAO; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems
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AN-YEU(ANDY) WU; Wu, A.-Y.; Huang, K.-K.; Lee, Y.-H.; Yu, T.-H. |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Ultra low-cost 3.2Gb/s optical-rate reed solomon decoder IC design
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Hsu, H.-Y.; Yeo, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
A robust band-tracking packet detector (BT-PD) in OFDM-based ultra-wideband systems
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Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
A triple-mode MAP/VA IP design for advanced wireless communication systems
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Lin, C.-H.; Li, F.-M.; Shi, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
DSP engine design for LINC wireless transmitter systems
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Jheng, K.-Y.; Wang, Y.-C.; Wu, A.-Y.; Tsao, H.-W.; AN-YEU(ANDY) WU |
Showing items 101-150 of 196 (4 Page(s) Totally)
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