| 臺大學術典藏 |
2018-09-10T05:59:22Z |
Multi-symbol-sliced dynamically reconfigurable reed-solomon decoder design based on unified finite-field processing element
|
Hsu, H.-Y.; Yeo, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:22Z |
On-line MSR-cordic VLSI architecture with applications to cost-efficient rotation-based adaptive filtering systems
|
Yu, T.-H.; Yu, C.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A low cost packet detector in OFDM-based ultra-wideband systems
|
Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A Shortened Impulse Response Filter (SIRF) scheme for cost-effective echo canceller design of 10GBase-T ethernet system
|
Hsu, M.-F.; Chen, Y.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:59:21Z |
A new early termination scheme of iterative turbo decoding using decoding threshold
|
Li, F.-M.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:52:05Z |
DSP engine design for LINC wireless transmitter systems
|
Jheng, K.-Y.; Wang, Y.-C.; Wu, A.-Y.; Tsao, H.-W.; HEN-WAI TSAO |
| 臺大學術典藏 |
2018-09-10T05:24:16Z |
Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
A scalable DCO design for portable ADPLL designs
|
Wu, C.-T.; Wang, W.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Digital signal processing engine design for polar transmitter in wireless communication systems
|
Ko, H.-Y.; Wang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Low cost decision feedback equalizer (DFE) design for giga-bit systems
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications
|
Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A DVB-T baseband demodulator design based on multimode silicon IPs
|
Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T. |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A memory-reduced Log-MAP kernel for turbo decoder
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Tsai, T.-H. |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme
|
Lin, C.-H.;Wu, A.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme
|
Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:06Z |
Multiplierless multirate decimator / interpolator module generator
|
Jou, S.-J.;Jheng, K.-Y.;Chen, H.-Y.;Wu, A.-Y.; Jou, S.-J.; Jheng, K.-Y.; Chen, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A design flow for multiplierless linear-phase fir filters: From system specification to verilog code
|
Jheng, K.-Y.; Jou, S.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design
|
Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
|
Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:32Z |
Implementation of a programmable 64?2048-point FFT/IFFT processor for OFDM-based communication systems
|
Kuo, J.-C.; Wen, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:32Z |
Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-perforance rotatioal operations
|
Lin, Z.-X.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:31Z |
A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation
|
Lai, J.-T.; Wu, A.-Y.; Yeh, C.-C.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:33:31Z |
Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems
|
AN-YEU(ANDY) WU; Chen, P.-H.; Kai-Huang; Hsueh, N.-H.; Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T04:13:19Z |
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
|
Hsu, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T04:13:19Z |
A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach
|
Wu, A.-Y.; Wu, C.-S.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T03:48:22Z |
An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter
|
Yu, C.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T03:48:21Z |
A novel Trellis-based searching scheme for EEAS-based CORDIC algorithm
|
Wu, C.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018 |
Impact of Supratentorial Cerebral Hemorrhage on the Complexity of Heart Rate Variability in Acute Stroke
|
Jeng J.-S.; Wu A.-Y.; Lai D.-M.; Shieh J.-S.; Lee D.-Y.; Tang S.-C.; CHIH-HAO CHEN |
| 臺大學術典藏 |
2017 |
Identification of Atrial Fibrillation by Quantitative Analyses of Fingertip Photoplethysmogram
|
Sung-Chun Tang;Huang P.-W.;Hung C.-S.;Shan S.-M.;Lin Y.-H.;Shieh J.-S.;Lai D.-M.;Wu A.-Y.;Jeng J.-S.; SUNG-CHUN TANG; Huang P.-W.; Hung C.-S.; Shan S.-M.; Lin Y.-H.; Shieh J.-S.; Lai D.-M.; Wu A.-Y.; Jeng J.-S. |
| 國立臺灣大學 |
2016 |
Impacts of Supratentorial Intracerebral Hemorrhage Locations on the Complexity of Heart Rate Variability
|
Chen, C. H.; Huang, P. W.; Tang, S. C.; Shieh, J. S.; Lai, D. M.; Wu, A. Y.; Jeng, J. S.; 鄭建興; 賴達明; 湯頌君; 陳珍信 |
| 國立臺灣大學 |
2015 |
Multiscale Entropy Analysis of Heart Rate Variability Can Predict Stroke-in-Evolution in Acute Ischemic Stroke Patients
|
Chen, C. H.; Tang, S. C.; Huang, P. W.; Lai, D. M.; Wu, A. Y.; Jeng, J. S.; 鄭建興; 賴達明; 湯頌君; 陳珍信 |
| 臺大學術典藏 |
2015 |
Predicting stroke outcomes based on multi-modal analysis of physiological signals
|
Huang P.-W.;Sung-Chun Tang;Lin Y.-M.;Liu Y.-C.;Jou W.-J.;Jen H.-I.;Lai D.-M.;Wu A.-Y.; Huang P.-W.; SUNG-CHUN TANG; Lin Y.-M.; Liu Y.-C.; Jou W.-J.; Jen H.-I.; Lai D.-M.; Wu A.-Y. |
| 臺大學術典藏 |
2014 |
A stroke severity monitoring system based on quantitative modified multiscale entropy
|
Wu A.-Y.; Lai D.-M.; SUNG-CHUN TANG; Huang P.-W.; Lin Y.-M.; Jou W.-J.; Jou W.-J.;Huang P.-W.;Lin Y.-M.;Sung-Chun Tang;Lai D.-M.;Wu A.-Y. |
| 臺大學術典藏 |
2013 |
Low-complexity sinusoidal-assisted EMD (SAEMD) algorithms for solving mode-mixing problems in HHT
|
Shen, W.-C.;Chen, Y.-H.;Wu, A.-Y.; Shen, W.-C.; Chen, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2012 |
Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Hung, H.-S.; Lin, S.-Y.; Chih-Hao; Chen, K.-C.; Chen, K.-C.;Chih-Hao;Lin, S.-Y.;Hung, H.-S.;Wu, A.-Y. |
| 臺大學術典藏 |
2011 |
Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding
|
Lin, C.-H.;Chen, C.-Y.;Wu, A.-Y.; Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2009 |
A channel-adaptive early termination strategy for LDPC decoders
|
Chen, Y.-H.;Chen, Y.-J.;Shih, X.-Y.;Wu, A.-Y.; Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2009 |
Welcome message from An-Yeu Wu, conference co-chair
|
Wu, A.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2008 |
A universal look-ahead algorithm for pipelining IIR filters
|
Chen, Y.-L.; Chen, C.-Y.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2008 |
Unified Convolutional/Turbo decoder design using tile-based timing analysis of VA/MAP kernel
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Li, F.-M. |
| 臺大學術典藏 |
2007 |
A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network
|
Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment
|
Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
High-performance VLSI architecture of decision feedback equalizer for gigabit systems
|
Lin, C.-H.; Wu, A.-Y.; Li, F.-M.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2001 |
Cost-efficient multiplier-less FIR filter structure based on modified decor transformation
|
Lee, I.-H.; Wu, C.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU |
