| 臺大學術典藏 |
2018-09-10T07:38:00Z |
PAC Duo SoC performance analysis with ESL design methodology
|
Chuang, I.-Y.;Chang, C.-W.;Fan, T.-Y.;Yeh, J.-C.;Ji, K.-M.;Ma, J.-L.;Wu, A.-Y.;Lin, S.-Y.; Chuang, I.-Y.; Chang, C.-W.; Fan, T.-Y.; Yeh, J.-C.; Ji, K.-M.; Ma, J.-L.; Wu, A.-Y.; Lin, S.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:59Z |
A scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems
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Lin, S.-Y.;Hsu, C.-C.;Wu, A.-Y.; Lin, S.-Y.; Hsu, C.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:59Z |
A triple-mode LDPC decoder design for IEEE 802.11n system
|
Chao, M.-A.;Wen, J.-Y.;Shih, X.-Y.;Wu, A.-Y.; Chao, M.-A.; Wen, J.-Y.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:58Z |
A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications
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AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Zhan, C.-Z.; Shih, X.-Y.; Shih, X.-Y.;Zhan, C.-Z.;Lin, C.-H.;Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T07:37:58Z |
A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices
|
Shih, X.-Y.;Zhan, C.-Z.;Wu, A.-Y.; Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Algorithm-based low-power transform coding architectures: The multirate approach
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Wu, A.-Y.; Liu, K.J.R.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
System architecture of an adaptive reconfigurable DSP computing engine
|
Wu, A.-Y.; Liu, K.J.R.; Raghupathy, A.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Overview of ITRI PAC project - From VLIW DSP processor to multicore computing platform
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Chu, Y.-H.; Lin, T.-J.; Liu, C.-N.; Tseng, S.-Y. |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-Balanced IP Mapping Algorithm for 2D-mesh on-chip-networks
|
Lin, T.-J.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-balanced routing algorithm for irregular mesh-based on-chip networks
|
Lin, S.-Y.; Huang, C.-H.; Chao, C.-H.; Huang, K.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Algorithm-based low-power and high-performance multimedia signal processing
|
Liu, K.J.R.; Wu, A.-Y.; Raghupathy, A.; Chen, J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-performance scheduling algorithm for partially parallel LDPC decoder
|
Zhan, C.-Z.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-throughput 12-mode CTC decoder for WiMAX standard
|
Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-throughput dual-mode single/double binary map processor design for wireless wan
|
Chen, C.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
Location-constrained particle filter for rssi-based indoor human positioning and tracking system
|
Chao, C.-H.; Chu, N.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
Low-power traceback MAP decoding for double-binary convolutional turbo decoder
|
Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
An 8.29 mm2 52 mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 μm CMOS process
|
Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation
|
Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system
|
Chen, Y.-L.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Cost-effective joint echo-NEXT canceller designs for 10GBase-T ethernet systems based on a shortened impulse response filter (SIRF) scheme
|
Chen, Y.-L.; Hsu, M.-F.; Lai, J.-T.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits
|
Wey, I.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:41Z |
A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications
|
AN-YEU(ANDY) WU; Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules
|
Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
On the fixed-point properties of mixed-scaling-rotation cordic algorithm
|
Yu, C.-L.; Yu, T.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
On the new stopping criteria of iterative turbo decoding by using decoding threshold
|
Li, F.-M.; Wu, A.-Y.; AN-YEU(ANDY) WU |
