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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
臺大學術典藏 2018-09-10T05:24:15Z Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T05:24:14Z A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T05:24:14Z A DVB-T baseband demodulator design based on multimode silicon IPs Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T05:24:14Z A high-speed scalable shift-register based on-chip serial communication design for SoC applications Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T.
臺大學術典藏 2018-09-10T05:24:14Z A memory-reduced Log-MAP kernel for turbo decoder AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Tsai, T.-H.
臺大學術典藏 2018-09-10T04:56:06Z Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme Lin, C.-H.;Wu, A.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:06Z High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:06Z Multiplierless multirate decimator / interpolator module generator Jou, S.-J.;Jheng, K.-Y.;Chen, H.-Y.;Wu, A.-Y.; Jou, S.-J.; Jheng, K.-Y.; Chen, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:05Z A design flow for multiplierless linear-phase fir filters: From system specification to verilog code Jheng, K.-Y.; Jou, S.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:05Z A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU

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