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Showing items 86-95 of 196 (20 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T08:43:20Z |
Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon
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Hsin, H.-K.;Chang, E.-J.;Chao, C.-H.;Lin, S.-Y.;Wu, A.-Y.; Hsin, H.-K.; Chang, E.-J.; Chao, C.-H.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:43:20Z |
Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part I: Hardware architecture & software development tools
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Wu, C.-J.; Lee, J.-K.; Chu, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU; Chang, D.C.-W.;Lin, T.-J.;Wu, C.-J.;Lee, J.-K.;Chu, Y.-H.;Wu, A.-Y.; Chang, D.C.-W.; Lin, T.-J. |
| 臺大學術典藏 |
2018-09-10T08:43:20Z |
Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part II: Application programming
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Chen, J.-M.;Liu, C.-N.;Yang, J.-K.;Tseng, S.-Y.;Shih, W.-K.;Wu, A.-Y.; Chen, J.-M.; Liu, C.-N.; Yang, J.-K.; Tseng, S.-Y.; Shih, W.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:43:20Z |
Traffic-and thermal-aware routing for throttled three-dimensional Network-on-Chip systems
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Lin, S.-Y.;Yin, T.-C.;Wang, H.-Y.;Wu, A.-Y.; Lin, S.-Y.; Yin, T.-C.; Wang, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:43:20Z |
Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems
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Chao, C.-H.;Yin, T.-C.;Lin, S.-Y.;Wu, A.-Y.; Chao, C.-H.; Yin, T.-C.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:43:19Z |
A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks
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Chen, K.-C.;Lin, S.-Y.;Shen, W.-C.;Wu, A.-Y.; Chen, K.-C.; Lin, S.-Y.; Shen, W.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:43:19Z |
Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems
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Zhan, C.-Z.;Liu, Z.-L.;Wu, A.-Y.; Zhan, C.-Z.; Liu, Z.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:43:19Z |
Design of transport layer assisted routing for thermal-aware 3D Network-on-Chip
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Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU; Yin, T.-C.;Chao, C.-H.;Lin, S.-Y.;Wu, A.-Y.; Yin, T.-C.; Chao, C.-H. |
| 臺大學術典藏 |
2018-09-10T08:43:18Z |
A 0.16nJ/bit/iteration 3.38mm 2 turbo decoder chip for WiMAX/LTE standards
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Lin, C.-H.;Chen, C.-Y.;Chang, E.-J.;Wu, A.-Y.; Lin, C.-H.; Chen, C.-Y.; Chang, E.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:40Z |
Traffic-thermal mutual-coupling co-simulation platform for three-dimensional network-on-chip
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Jheng, K.-Y.;Chao, C.-H.;Wang, H.-Y.;Wu, A.-Y.; Jheng, K.-Y.; Chao, C.-H.; Wang, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
Showing items 86-95 of 196 (20 Page(s) Totally)
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