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Institution Date Title Author
國立交通大學 2014-12-08T15:30:02Z A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement Lee, Yu-Huei; Peng, Shen-Yu; Chiu, Chao-Chang; Wu, Alex Chun-Hsien; Chen, Ke-Horng; Lin, Ying-Hsi; Wang, Shih-Wei; Tsai, Tsung-Yen; Huang, Chen-Chih; Lee, Chao-Cheng

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