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Taiwan Academic Institutional Repository >
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"wu an yeu"
Showing items 36-60 of 109 (5 Page(s) Totally)
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| 臺大學術典藏 |
2009 |
Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits
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Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu; Chen, Jie; Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu; Chen, Jie |
| 臺大學術典藏 |
2009 |
Adaptive Channel-Shortened Interpolated Echo and NEXT Canceller Designs Applied to 10GBASE-T Ethernet System
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Chen, Yen-Liang; Zhan, Cheng-Zhou; Jheng, Ting-Jyun; Wu, An-Yeu; Chen, Yen-Liang; Zhan, Cheng-Zhou; Jheng, Ting-Jyun; Wu, An-Yeu |
| 臺大學術典藏 |
2009 |
Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor
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Lin, Shu-Yen; Shen, Wen-Chung; Hsu, Chan-Cheng; Wu, An-Yeu; Lin, Shu-Yen; Shen, Wen-Chung; Hsu, Chan-Cheng; Wu, An-Yeu |
| 國立臺灣大學 |
2008 |
An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 μm CMOS Process
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Shih, Xin-Yu; Zhan, Cheng-Zhou; Lin, Cheng-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2008 |
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
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Lin, Shu-Yen; Huang, Chun-Hsiang; Chao, Chih-Hao; Huang, Keng-Hsien; Wu, An-Yeu |
| 國立臺灣大學 |
2008 |
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
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Li, Fan-Min; Lin, Cheng-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2008 |
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits
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Wey, I-Chyn; Chen, You-Gang; Wu, An-Yeu |
| 臺大學術典藏 |
2007-04-19T04:55:08Z |
A new stopping criterion for efficient early termination in turbo decoder designs
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Li, F.-M. and Wu, A.-Y.; Li, Fan-Min; Wu, An-Yeu; Li, Fan-Min; Wu, An-Yeu |
| 國立臺灣大學 |
2007 |
Joint AGC-Equalization (Joint AGC-EQ) Algorithm and VLSI Architecture For Wirelined Transceiver Designs
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Lai, Jyh-Ting; Wu, An-Yeu; Lee, Chien-Hsiung |
| 國立臺灣大學 |
2007 |
A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultrawideband Systems
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Lai, Jyh-Ting; Wu, An-Yeu; Chen, Wen-Chiang |
| 國立臺灣大學 |
2007 |
On The New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold
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Li, Fan-Min; Wu, An-Yeu |
| 國立臺灣大學 |
2006-05 |
A portable all-digital pulsewidth control loop for SOC applications
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Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu |
| 國立臺灣大學 |
2006-05 |
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 臺大學術典藏 |
2006-05 |
A portable all-digital pulsewidth control loop for SOC applications
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Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu; Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu |
| 臺大學術典藏 |
2006-05 |
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu; Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed–Solomon Decoder Design Based on Unified Finite-Field Processing Element
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Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
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Lin, Chih-Hsiu; Wu, An-Yeu; Li, Fan-Min |
| 國立臺灣大學 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-12 |
A new stopping criterion for efficient early termination in turbo decoder designs
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Li, Fan-Min; Wu, An-Yeu |
| 臺大學術典藏 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu; Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-07 |
A high speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chen, You-Gang; Wu, Chia-Tsun; Wang, Wei; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A scalable DCO design for portable ADPLL designs
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chang, Lung-Hao; Chen, You-Gang; Chang, Shih-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
Digital signal processing engine design for polar transmitter in wireless communication systems
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Ko, Hung-Yang; Wang, Yi-Chiuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-03 |
Low cost decision feedback equalizer (DFE) design for Giga-bit systems
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Lin, Chih-Hsiu; Wu, An-Yeu |
Showing items 36-60 of 109 (5 Page(s) Totally)
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