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Taiwan Academic Institutional Repository >
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"wu an yeu"
Showing items 41-65 of 109 (5 Page(s) Totally) << < 1 2 3 4 5 > >> View [10|25|50] records per page
| 國立臺灣大學 |
2008 |
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
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Li, Fan-Min; Lin, Cheng-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2008 |
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits
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Wey, I-Chyn; Chen, You-Gang; Wu, An-Yeu |
| 臺大學術典藏 |
2007-04-19T04:55:08Z |
A new stopping criterion for efficient early termination in turbo decoder designs
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Li, F.-M. and Wu, A.-Y.; Li, Fan-Min; Wu, An-Yeu; Li, Fan-Min; Wu, An-Yeu |
| 國立臺灣大學 |
2007 |
Joint AGC-Equalization (Joint AGC-EQ) Algorithm and VLSI Architecture For Wirelined Transceiver Designs
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Lai, Jyh-Ting; Wu, An-Yeu; Lee, Chien-Hsiung |
| 國立臺灣大學 |
2007 |
A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultrawideband Systems
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Lai, Jyh-Ting; Wu, An-Yeu; Chen, Wen-Chiang |
| 國立臺灣大學 |
2007 |
On The New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold
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Li, Fan-Min; Wu, An-Yeu |
| 國立臺灣大學 |
2006-05 |
A portable all-digital pulsewidth control loop for SOC applications
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Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu |
| 國立臺灣大學 |
2006-05 |
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 臺大學術典藏 |
2006-05 |
A portable all-digital pulsewidth control loop for SOC applications
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Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu; Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu |
| 臺大學術典藏 |
2006-05 |
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu; Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed–Solomon Decoder Design Based on Unified Finite-Field Processing Element
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Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
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Lin, Chih-Hsiu; Wu, An-Yeu; Li, Fan-Min |
| 國立臺灣大學 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-12 |
A new stopping criterion for efficient early termination in turbo decoder designs
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Li, Fan-Min; Wu, An-Yeu |
| 臺大學術典藏 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu; Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-07 |
A high speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chen, You-Gang; Wu, Chia-Tsun; Wang, Wei; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A scalable DCO design for portable ADPLL designs
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chang, Lung-Hao; Chen, You-Gang; Chang, Shih-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
Digital signal processing engine design for polar transmitter in wireless communication systems
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Ko, Hung-Yang; Wang, Yi-Chiuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-03 |
Low cost decision feedback equalizer (DFE) design for Giga-bit systems
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Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2005 |
Soft-Threshold-Based MultiLayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture
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Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
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Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
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Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
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Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
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Hsu, H.-Y. and Yeo, J.-C. and Wu, A.-Y.; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
Showing items 41-65 of 109 (5 Page(s) Totally) << < 1 2 3 4 5 > >> View [10|25|50] records per page
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