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显示项目 11-35 / 109 (共5页)
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机构 日期 题名 作者
臺大學術典藏 2020-02-27T09:39:43Z Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems Chang, En-Jui;Hsin, Hsien-Kai;Lin, Shu-Yen;Wu, An-Yeu; Chang, En-Jui; Hsin, Hsien-Kai; Lin, Shu-Yen; Wu, An-Yeu; SHU-YEN LIN
臺大學術典藏 2018-09-10T07:38:01Z Scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T07:04:46Z Transform-domain delayed LMS algorithm and architecture Wu, An-Yeu; Wu, Cheng-Shing; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T07:04:45Z Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T07:04:45Z Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T07:04:45Z Fast algorithm for reduced-complexity programmable DSP implementation of the IFFT/FFT in DMT systems Wu, An-Yeu; Chan, Tsun-Shan; Wang, Bowen; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T07:04:45Z Optimal fixed-point VLSI structure of a floating-point based digital filter design Wu, An-Yeu; Hwang, Kuo-Fuo; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T05:59:23Z Low-power design methodology for DSP systems using multirate approach Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU; Wu, An-Yeu;Ray Liu, K.J.;Zhang, Zhongying;Nakajima, Kazuo;Raghupathy, Arun
臺大學術典藏 2018-09-10T05:24:16Z Algorithm-based low-power DSP system design: Methodology and verification Wu, An-Yeu;Liu, K.J.Ray;Zhang, Zhongying;Nakajima, Kazuo;Raghupathy, Arun;Liu, Shang-Chieh; Wu, An-Yeu; Liu, K.J.Ray; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T05:24:16Z Algorithm-based low-power transform coding architectures Wu, An-Yeu;Liu, K.J.Ray; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:07Z Algorithms and architectures for split recursive least squares Liu, K.J.Ray;Wu, An-Yeu; Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:56:07Z Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:33:32Z Multi-layer 2-D adaptive filtering architecture based on McClellan transformation Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T04:33:31Z A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes Wu, Cheng-Shing; Wu, An-Yeu; Lin, Chih-Hsiu; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T03:30:01Z Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU
臺大學術典藏 2018-09-10T03:30:01Z Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT Wu, Cheng-Shing; Wu, An-Yeu; AN-YEU(ANDY) WU
臺大學術典藏 2018-07-06T09:46:46Z A new pipelined adaptive DFE architecture with improved convergence rate Wu, An-Yeu; Yang, Meng-Da; Yang, Meng-Da; Wu, An-Yeu
國立臺灣大學 2015 Complexity of heart rate variability predicts outcome in intensive care unit admitted patients with acute stroke Tang, Sung-Chun; Jen, Hsiao-I; Lin, Yen-Hung; Hung, Chi-Sheng; Jou, Wei-Jung; Huang, Pei-Wen; Shieh, Jiann-Shing; Ho, Yi-Lwun; Lai, Dar-Ming; Wu, An-Yeu; Jeng, Jiann-Shing; Chen, Ming-Fong; 鄭建興; 林彥宏; 賴達明; 洪啟盛; 陳明豐; 湯頌君; 何奕倫
國立臺灣大學 2015 Effect of mannitol on cerebrovascular pressure reactivity in patients with intracranial hypertension Tang, Sung-Chun; Lin, Ru-Jen; Shieh, Jiann-Shing; Wu, An-Yeu; Lai, Dar-Ming; Huang, Sheng-Jean; Jeng, Jiann-Shing; 黃勝堅; 鄭建興; 賴達明; 湯頌君
國立交通大學 2014-12-08T15:12:02Z Parallel Architecture Core (PAC)-the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools Chang, David Chih-Wei; Lin, Tay-Jyi; Wu, Chung-Ju; Lee, Jenq-Kuen; Chu, Yuan-Hua; Wu, An-Yeu
國立臺灣大學 2009 Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu; Chen, Jie
國立臺灣大學 2009 Multilevel LINC system designs for power efficiency enhancement of transmitters Jheng, Kai-Yuan; Chen, Yuan-Jyue; Wu, An-Yeu
國立臺灣大學 2009 Adaptive Channel-Shortened Interpolated Echo and NEXT Canceller Designs Applied to 10GBASE-T Ethernet System Chen, Yen-Liang; Zhan, Cheng-Zhou; Jheng, Ting-Jyun; Wu, An-Yeu
國立臺灣大學 2009 Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor Lin, Shu-Yen; Shen, Wen-Chung; Hsu, Chan-Cheng; Wu, An-Yeu
國立臺灣大學 2009 Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder Lin, Cheng-Hung; Chen, Chun-Yu; Tsai, Tsung-Han; Wu, An-Yeu

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