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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"wu an yeu"的相关文件
显示项目 71-80 / 109 (共11页)
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| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
|
Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
|
Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 國立臺灣大學 |
2004 |
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
|
Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 臺大學術典藏 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
|
Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu; Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
| 國立臺灣大學 |
2003-09 |
Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems
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Chen, Pen-Hsin; Kai-Huang; Hsueh, Nai-Hsuan; Wu, An-Yeu |
| 國立臺灣大學 |
2003-08 |
A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation
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Lai, Jyh-Ting; Wu, An-Yeu; Yeh, Cheng-Chung |
| 國立臺灣大學 |
2003-05 |
Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems
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Kuo, Jen-Chih; Wen, Ching-Hua; Wu, An-Yeu |
显示项目 71-80 / 109 (共11页)
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