| 國立臺灣大學 |
2005-07 |
A high speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wey, I-Chyn; Chen, You-Gang; Wu, Chia-Tsun; Wang, Wei; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A scalable DCO design for portable ADPLL designs
|
Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
|
Wey, I-Chyn; Chang, Lung-Hao; Chen, You-Gang; Chang, Shih-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
Digital signal processing engine design for polar transmitter in wireless communication systems
|
Ko, Hung-Yang; Wang, Yi-Chiuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-03 |
Low cost decision feedback equalizer (DFE) design for Giga-bit systems
|
Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2005 |
Soft-Threshold-Based MultiLayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture
|
Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, H.-Y. and Yeo, J.-C. and Wu, A.-Y.; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
|
Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
|
Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
|
Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu; Wen, Ching-Hua; Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
|
Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu; Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
|
Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
|
Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 國立臺灣大學 |
2004 |
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
|
Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 臺大學術典藏 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
|
Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu; Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
| 國立臺灣大學 |
2003-09 |
Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems
|
Chen, Pen-Hsin; Kai-Huang; Hsueh, Nai-Hsuan; Wu, An-Yeu |
| 國立臺灣大學 |
2003-08 |
A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation
|
Lai, Jyh-Ting; Wu, An-Yeu; Yeh, Cheng-Chung |
| 國立臺灣大學 |
2003-05 |
Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems
|
Kuo, Jen-Chih; Wen, Ching-Hua; Wu, An-Yeu |
