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"wu an yeu"的相關文件
顯示項目 66-75 / 109 (共11頁)
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| 國立臺灣大學 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
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Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
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Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
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Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
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Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu; Wen, Ching-Hua; Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
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Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu; Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
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Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
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Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
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Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
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Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 國立臺灣大學 |
2004 |
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
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Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
顯示項目 66-75 / 109 (共11頁)
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