|
"wu an yeu"的相關文件
顯示項目 61-70 / 109 (共11頁)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
每頁顯示[10|25|50]項目
| 國立臺灣大學 |
2005 |
Soft-Threshold-Based MultiLayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture
|
Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, H.-Y. and Yeo, J.-C. and Wu, A.-Y.; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
|
Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
|
Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
|
Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu; Wen, Ching-Hua; Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
|
Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu; Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
顯示項目 61-70 / 109 (共11頁)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
每頁顯示[10|25|50]項目
|
