|
"wu chung yu"的相關文件
顯示項目 206-219 / 219 (共5頁) << < 1 2 3 4 5 每頁顯示[10|25|50]項目
| 國立彰化師範大學 |
2009-05 |
Investigation of C-reactive Protein Binding to Phosphatidyl Choline by CZE and ESI-Mass Analysis
|
Peng, Yu-Non; Ho, Yu-Ling; Wu, Chung-Yu; Liu, Mine-Yine |
| 國立彰化師範大學 |
2008-11 |
In Vitro Oxidized and Glycated Human Low-density Lipoprotein Particles Characterized by Capillary Zone Electrophoresis
|
Chiu, Jing-Huei; Peng, Yu-Nong; Yang, Ying-Ling; Tsai, Ming-Hua; Ho, Yu-Ling; Wu, Chung-Yu; Liu, Mine-Yine |
| 國立臺灣大學 |
2008 |
以粒線體序列分析桃園豬、蘭嶼豬遺傳歧異度與其他外來豬種間之親緣關係
|
吳宗育; Wu, Chung-Yu |
| 國立彰化師範大學 |
2007-08 |
Separation and Determination of in Vitro Oxidized Phospholipids by Capillary Zone Electrophoresis
|
Ho, Yu-Ling; Chiu, Jing-Huei; Wu, Chung-Yu; Liu, Mine-Yine |
| 淡江大學 |
2007 |
兒童圖書館閱覽座椅使用現況之研究-從人因觀點切入
|
伍崇毓; Wu, Chung-yu |
| 淡江大學 |
1996-05 |
True-single-phase all-N-logic differential logic (TADL) for very high-speed complex VLSI
|
Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Chu, Yuan-hua; Wu, Chung-yu |
| 淡江大學 |
1995-04-30 |
Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits
|
Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan; Chu, Yuan-hua; Wu, Tain-shun; Wu, Chung-yu |
| 淡江大學 |
1995-04-30 |
A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
|
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Lu, Jr-houng |
| 淡江大學 |
1994-05-30 |
Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
|
Tseng, Yuh-kuang; 鄭國興; Cheng, Kuo-hsing; Wu, Chung-yu |
| 淡江大學 |
1993-01 |
Analysis and design of a new race-free four-phase CMOS logic
|
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan |
| 淡江大學 |
1992-05 |
High-speed four-phase CMOS logic for complex high-speed VLSI
|
Wu, Chung-yu; Cheng, Kuo-hsing; Wang, Jinn-shyan |
| 淡江大學 |
1991-09 |
Latched CMOS differential logic(LCDL)for complex high-speed VLSI
|
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing |
| 淡江大學 |
1989-09 |
Latched CMOS differential logic(LCDL)for complex high-speed VLSI
|
Wu, Chung-yu; Cheng, Kuo-hsing |
| 淡江大學 |
1912-01 |
Latched CMOS differential logic(ALCDL)and its application in the design of high-speed parallel multipliers
|
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing |
顯示項目 206-219 / 219 (共5頁) << < 1 2 3 4 5 每頁顯示[10|25|50]項目
|