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"wu cy"
Showing items 286-310 of 607 (25 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:06:22Z |
A HIGH-DENSITY MOS STATIC RAM CELL USING THE LAMBDA BIPOLAR-TRANSISTOR
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WU, CY; LIU, YF |
| 國立交通大學 |
2014-12-08T15:06:21Z |
A NEW HIGH-POWER VOLTAGE-CONTROLLED DIFFERENTIAL NEGATIVE-RESISTANCE DEVICE - THE LAMBDA-BIPOLAR POWER TRANSISTOR
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WU, CY; LEE, CS |
| 國立交通大學 |
2014-12-08T15:06:21Z |
THE EFFECT OF THE MINORITY-CARRIER DISTRIBUTION ON THE THRESHOLD VOLTAGE OF A MOSFET
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WU, CY; CHIEN, HC |
| 國立交通大學 |
2014-12-08T15:06:20Z |
A NEW INTERNAL OVERVOLTAGE PROTECTION STRUCTURE FOR THE BIPOLAR POWER TRANSISTOR
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WU, CY |
| 國立交通大學 |
2014-12-08T15:06:19Z |
A NEW DYNAMIC RANDOM-ACCESS MEMORY CELL USING A BIPOLAR MOS COMPOSITE STRUCTURE
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WU, CY |
| 國立交通大學 |
2014-12-08T15:06:19Z |
A NEW COMPUTER-AIDED SIMULATION-MODEL FOR POLYCRYSTALLINE SILICON FILM RESISTORS
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WU, CY; KEN, WD |
| 國立交通大學 |
2014-12-08T15:06:17Z |
AN ANALYTIC AND ACCURATE MODEL FOR THE THRESHOLD VOLTAGE OF SHORT CHANNEL MOSFETS IN VLSI
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WU, CY; YANG, SY; CHEN, HH; TSENG, FC; SHIH, CT |
| 國立交通大學 |
2014-12-08T15:06:16Z |
THE METAL-INSULATOR-SEMICONDUCTOR-SWITCH (MISS) DEVICE USING THERMAL NITRIDE FILM AS THE TUNNELING INSULATOR
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WU, CY; HUANG, YT |
| 國立交通大學 |
2014-12-08T15:06:15Z |
AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES
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WU, CY; HWANG, JS; CHANG, C; CHANG, CC |
| 國立交通大學 |
2014-12-08T15:06:15Z |
A NEW APPROACH TO MODEL CMOS LATCHUP
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WU, CY; YANG, YH; CHANG, C; CHANG, CC |
| 國立交通大學 |
2014-12-08T15:06:15Z |
A SIMPLE PUNCHTHROUGH VOLTAGE MODEL FOR SHORT-CHANNEL MOSFETS WITH SINGLE CHANNEL IMPLANTATION IN VLSI
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WU, CY; HSIAO, WZ; CHEN, HH |
| 國立交通大學 |
2014-12-08T15:06:15Z |
A NEW METHOD FOR COMPUTER-AIDED OPTIMIZATION OF SOLAR-CELL STRUCTURES
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CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:15Z |
A STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTION
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CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:13Z |
THE LAMBDA-BIPOLAR PHOTOTRANSISTOR ANALYSIS AND APPLICATIONS
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WU, CY; SHENG, HD; TSAI, YT |
| 國立交通大學 |
2014-12-08T15:06:13Z |
AN ACCURATE AND ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY MOSFETS WITH SINGLE-CHANNEL ION-IMPLANTATION IN VLSI
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WU, CY; HUANG, GS; CHEN, HH; TSENG, FC; SHIH, CT |
| 國立交通大學 |
2014-12-08T15:06:13Z |
AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATION
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WU, CY; DAIH, YW |
| 國立交通大學 |
2014-12-08T15:06:13Z |
A NEW THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY BURIED-CHANNEL MOSFETS
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WU, CY; HSU, KC |
| 國立交通大學 |
2014-12-08T15:06:13Z |
MOBILITY MODELS FOR THE IV CHARACTERISTICS OF BURIED-CHANNEL MOSFETS
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WU, CY; HSU, KC |
| 國立交通大學 |
2014-12-08T15:06:12Z |
SUPERIOR CHARACTERISTICS OF NITRIDIZED THERMAL OXIDE GROWN ON POLYCRYSTALLINE SILICON
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CHEN, CF; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN EFFICIENT METHOD FOR CALCULATING THE DC TRIGGERING CURRENTS IN CMOS LATCH-UP
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CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:11Z |
A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES
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CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATION
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WU, CY; HUANG, GS; CHEN, HH |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS
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CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
AN ENVIRONMENT-INSENSITIVE TRILAYER STRUCTURE FOR TITANIUM SILICIDE FORMATION
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LIN, MZ; YU, YCS; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
A CHARACTERIZATION MODEL FOR RAMP-VOLTAGE-STRESSED IV CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE
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CHEN, CF; WU, CY |
Showing items 286-310 of 607 (25 Page(s) Totally)
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