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"wu cy"
Showing items 351-400 of 607 (13 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:05:32Z |
AN ANALYTIC SATURATION MODEL FOR DRAIN AND SUBSTRATE CURRENTS OF CONVENTIONAL AND LDD MOSFETS
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HUANG, GS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:32Z |
EXCELLENT THERMAL-STABILITY OF COBALT ALUMINUM-ALLOY SCHOTTKY CONTACTS ON GAAS SUBSTRATES
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CHENG, HC; WU, CY; SHY, JJ |
| 國立交通大學 |
2014-12-08T15:05:30Z |
EFFICIENT PHYSICAL TIMING MODELS FOR CMOS AND-OR-INVERTER AND OR-AND-INVERTER GATES AND THEIR APPLICATIONS
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WU, CY; SHIAU, MC |
| 國立交通大學 |
2014-12-08T15:05:27Z |
REALIZATIONS OF IIR/FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE
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YU, TC; WU, CY; CHANG, SC |
| 國立交通大學 |
2014-12-08T15:05:27Z |
DELAY MODELS AND SPEED IMPROVEMENT TECHNIQUES FOR RC TREE INTERCONNECTIONS AMONG SMALL-GEOMETRY CMOS INVERTERS
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WU, CY; SHIAU, MC |
| 國立交通大學 |
2014-12-08T15:05:25Z |
PHYSICAL TIMING MODELS AND DESIGN METHODOLOGY OF BIPOLAR NONTHRESHOLD LOGIC-CIRCUITS
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WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:17Z |
NEW PHYSICAL TIMING MODELS OF BIPOLAR NONSATURATION LOGIC USING CURRENT DOMAIN ANALYSIS TECHNIQUE
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WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:15Z |
EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS
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HWANG, JS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:14Z |
A NEW METHODOLOGY FOR DEVELOPING A FAST 2-DIMENSIONAL MOSFET DEVICE SIMULATOR
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PERNG, RK; LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:13Z |
A NEW SIMPLIFIED 2-DIMENSIONAL MODEL FOR THE THRESHOLD VOLTAGE OF MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE
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LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:10Z |
LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI
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WU, CY; CHENG, KH |
| 國立交通大學 |
2014-12-08T15:05:08Z |
DESIGN TECHNIQUES FOR HIGH-FREQUENCY CMOS SWITCHED-CAPACITOR FILTERS USING NON-OP-AMP-BASED UNITY-GAIN AMPLIFIERS
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WU, CY; LU, PH; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:04:59Z |
A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
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WU, CY; KER, MD; LEE, CY; KO, J |
| 國立交通大學 |
2014-12-08T15:04:54Z |
PHYSICAL MODEL FOR CHARACTERIZING AND SIMULATING A FLOTOX EEPROM DEVICE
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WU, CY; CHEN, CF |
| 國立交通大學 |
2014-12-08T15:04:49Z |
THE PROCESS WINDOW OF A-SI/TI BILAYER METALLIZATION FOR AN OXIDATION-RESISTANT AND SELF-ALIGNED TISI2 PROCESS
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LOU, YS; WU, CY; CHENG, HC |
| 國立交通大學 |
2014-12-08T15:04:49Z |
A NEW 2-DIMENSIONAL MODEL FOR THE POTENTIAL DISTRIBUTION OF SHORT GATE-LENGTH MESFETS AND ITS APPLICATIONS
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CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:48Z |
HIGH-PRECISION CURVATURE-COMPENSATED CMOS BAND-GAP VOLTAGE AND CURRENT REFERENCES
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WU, CY; CHIN, SY |
| 國立交通大學 |
2014-12-08T15:04:48Z |
NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONS
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HWANG, JS; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:43Z |
A NEW METHODOLOGY FOR 2-DIMENSIONAL NUMERICAL-SIMULATION OF SEMICONDUCTOR-DEVICES
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CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:41Z |
ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGIC
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WU, CY; CHENG, KH; WANG, JS |
| 國立交通大學 |
2014-12-08T15:04:41Z |
A NEW OXIDATION-RESISTANT COSI2 PROCESS FOR SELF-ALIGNED SILICIDATION (SALICIDE) TECHNOLOGY
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LOU, YS; WU, CY; CHENG, HC |
| 國立交通大學 |
2014-12-08T15:04:34Z |
A NEW IV MODEL FOR SHORT GATE-LENGTH MESFETS
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CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:25Z |
DESIGN AND APPLICATION OF PIPELINED DYNAMIC CMOS TERNARY LOGIC AND SIMPLE TERNARY DIFFERENTIAL LOGIC
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WU, CY; HUANG, HY |
| 國立交通大學 |
2014-12-08T15:04:23Z |
A NEW GRID-GENERATION METHOD FOR 2-D SIMULATION OF DEVICES WITH NONPLANAR SEMICONDUCTOR SURFACE
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CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:22Z |
A NEW 2D ANALYTIC THRESHOLD-VOLTAGE MODEL FOR FULLY DEPLETED SHORT-CHANNEL SOI MOSFETS
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GUO, JY; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:22Z |
THE DESIGN OF FULLY DIFFERENTIAL CMOS OPERATIONAL-AMPLIFIERS WITHOUT EXTRA COMMON-MODE FEEDBACK-CIRCUITS
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LU, PH; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:04:20Z |
A NOVEL PHL-EMITTER BIPOLAR-TRANSISTOR - FABRICATION AND CHARACTERIZATION
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CHANG, KZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:12Z |
NOVEL CHARACTERISTICS OF THE POLYSILICON HIGH-LOW-EMITTER (PHL-EMITTER) BIPOLAR-TRANSISTOR HIGH-CURRENT GAIN AND ZERO ACTIVATION-ENERGY
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CHANG, KZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:11Z |
CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:09Z |
TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:09Z |
A CHARACTERIZATION TECHNIQUE FOR THE DEGRADATION CHARACTERISTICS OF TI/SI SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS AFTER THERMAL SILICIDATION
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:08Z |
COMPARATIVE-STUDIES OF GD-ORDERING IN VARIOUS CUPRATE SYSTEMS
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HO, JC; WU, CY; LAI, CC; SHIEH, JH; KU, HC |
| 國立交通大學 |
2014-12-08T15:04:08Z |
MAGNETIC-BEHAVIOR IN PR-CONTAINING TL-BASED AND PB-BASED CUPRATES
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KU, HC; LAI, CC; SHIEH, JH; LIOU, JW; WU, CY; HO, JC |
| 國立交通大學 |
2014-12-08T15:04:02Z |
A SELF-CONSISTENT CHARACTERIZATION METHODOLOGY FOR SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:57Z |
NEW DESIGN METHODOLOGY AND NEW DIFFERENTIAL LOGIC-CIRCUITS FOR THE IMPLEMENTATION OF TERNARY LOGIC SYSTEMS IN CMOS-VLSI WITHOUT PROCESS MODIFICATION
|
HUANG, HY; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:43Z |
A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
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CHIN, SY; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:41Z |
REALIZATIONS OF HIGH-ORDER SWITCHED-CAPACITOR FILTERS USING MULTIPLEXING TECHNIQUE
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WU, CY; BOR, JC; JENG, BS |
| 國立交通大學 |
2014-12-08T15:03:37Z |
THE EFFECTS OF IMPURITY BANDS ON THE ELECTRICAL CHARACTERISTICS OF METAL-SEMICONDUCTOR OHMIC CONTACTS
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:37Z |
NEW DESIGN TECHNIQUES FOR A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CURRENT READOUT INTEGRATED-CIRCUIT FOR INFRARED DETECTOR ARRAYS
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WU, CY; HSIEH, CC |
| 國立交通大學 |
2014-12-08T15:03:36Z |
A LOW GLITCH 10-BIT 75-MHZ CMOS VIDEO D/A CONVERTER
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WU, TY; JIH, CT; CHEN, JC; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:36Z |
PRECISE CMOS CURRENT SAMPLE HOLD CIRCUITS USING DIFFERENTIAL CLOCK FEEDTHROUGH ATTENUATION TECHNIQUES
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WU, CY; CHEN, CC; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:03:30Z |
LATERAL TITANIUM SILICIDE GROWTH AND ITS SUPPRESSION USING THE A-SI/TI BILAYER STRUCTURE
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:27Z |
A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION
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WEN, KS; LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:25Z |
A NOVEL EXTRACTION TECHNIQUE FOR THE EFFECTIVE CHANNEL-LENGTH OF MOSFET DEVICES
|
LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:24Z |
A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES
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WU, CY; CHEN, CC; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:03:22Z |
CMOS CURRENT-MODE IMPLEMENTATION OF SPATIOTEMPORAL PROBABILISTIC NEURAL NETWORKS FOR SPEECH RECOGNITION
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WU, CY; LIU, RY; JOU, IC |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:17Z |
A NEW CONSTANT-FIELD SCALING THEORY FOR MOSFETS
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MAA, JJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:16Z |
COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS
|
KER, MD; WU, CY |
Showing items 351-400 of 607 (13 Page(s) Totally)
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View [10|25|50] records per page
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