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Taiwan Academic Institutional Repository >
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"wu cy"
Showing items 381-405 of 607 (25 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:04:09Z |
A CHARACTERIZATION TECHNIQUE FOR THE DEGRADATION CHARACTERISTICS OF TI/SI SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS AFTER THERMAL SILICIDATION
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:08Z |
COMPARATIVE-STUDIES OF GD-ORDERING IN VARIOUS CUPRATE SYSTEMS
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HO, JC; WU, CY; LAI, CC; SHIEH, JH; KU, HC |
| 國立交通大學 |
2014-12-08T15:04:08Z |
MAGNETIC-BEHAVIOR IN PR-CONTAINING TL-BASED AND PB-BASED CUPRATES
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KU, HC; LAI, CC; SHIEH, JH; LIOU, JW; WU, CY; HO, JC |
| 國立交通大學 |
2014-12-08T15:04:02Z |
A SELF-CONSISTENT CHARACTERIZATION METHODOLOGY FOR SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:57Z |
NEW DESIGN METHODOLOGY AND NEW DIFFERENTIAL LOGIC-CIRCUITS FOR THE IMPLEMENTATION OF TERNARY LOGIC SYSTEMS IN CMOS-VLSI WITHOUT PROCESS MODIFICATION
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HUANG, HY; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:43Z |
A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
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CHIN, SY; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:41Z |
REALIZATIONS OF HIGH-ORDER SWITCHED-CAPACITOR FILTERS USING MULTIPLEXING TECHNIQUE
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WU, CY; BOR, JC; JENG, BS |
| 國立交通大學 |
2014-12-08T15:03:37Z |
THE EFFECTS OF IMPURITY BANDS ON THE ELECTRICAL CHARACTERISTICS OF METAL-SEMICONDUCTOR OHMIC CONTACTS
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:37Z |
NEW DESIGN TECHNIQUES FOR A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CURRENT READOUT INTEGRATED-CIRCUIT FOR INFRARED DETECTOR ARRAYS
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WU, CY; HSIEH, CC |
| 國立交通大學 |
2014-12-08T15:03:36Z |
A LOW GLITCH 10-BIT 75-MHZ CMOS VIDEO D/A CONVERTER
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WU, TY; JIH, CT; CHEN, JC; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:36Z |
PRECISE CMOS CURRENT SAMPLE HOLD CIRCUITS USING DIFFERENTIAL CLOCK FEEDTHROUGH ATTENUATION TECHNIQUES
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WU, CY; CHEN, CC; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:03:30Z |
LATERAL TITANIUM SILICIDE GROWTH AND ITS SUPPRESSION USING THE A-SI/TI BILAYER STRUCTURE
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:27Z |
A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION
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WEN, KS; LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:25Z |
A NOVEL EXTRACTION TECHNIQUE FOR THE EFFECTIVE CHANNEL-LENGTH OF MOSFET DEVICES
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LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:24Z |
A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES
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WU, CY; CHEN, CC; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:03:22Z |
CMOS CURRENT-MODE IMPLEMENTATION OF SPATIOTEMPORAL PROBABILISTIC NEURAL NETWORKS FOR SPEECH RECOGNITION
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WU, CY; LIU, RY; JOU, IC |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:17Z |
A NEW CONSTANT-FIELD SCALING THEORY FOR MOSFETS
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MAA, JJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:16Z |
COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:16Z |
A SIMPLE AND ACCURATE SIMULATION TECHNIQUE FOR FLASH EEPROM WRITING AND ITS RELIABILITY ISSUE
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WEN, KS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:14Z |
A NEW SIMPLIFIED THRESHOLD-VOLTAGE MODEL FOR N-MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE AND ITS APPLICATION TO MOSFETS MINIATURIZATION
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MAA, JJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:14Z |
A NEW STRUCTURE OF THE 2-D SILICON RETINA
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WU, CY; CHIU, CF |
| 國立交通大學 |
2014-12-08T15:03:12Z |
A CMOS CURRENT-MODE DESIGN OF MODIFIED LEARNING-VECTOR-QUANTIZATION NEURAL NETWORKS
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LIU, RY; WU, CY; JOU, IC |
| 國立交通大學 |
2014-12-08T15:03:01Z |
A 2-D ANALYTIC MODEL FOR THE THRESHOLD-VOLTAGE OF FULLY DEPLETED SHORT GATE-LENGTH SI-SOI MESFETS
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HOU, CS; WU, CY |
Showing items 381-405 of 607 (25 Page(s) Totally)
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