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"wu cy"的相关文件
显示项目 206-230 / 607 (共25页)
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| 國立交通大學 |
2014-12-08T15:27:47Z |
A 3-V 1-GHz low-noise bandpass amplifier
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WU, CY; HSIAO, SY; LIU, RY |
| 國立交通大學 |
2014-12-08T15:27:46Z |
A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
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WU, CY; CHENG, KH; LU, JH |
| 國立交通大學 |
2014-12-08T15:27:46Z |
The design of new low-voltage CMOS VHF continuous-time lowpass biquad filters
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WU, CY; HSU, HS |
| 國立交通大學 |
2014-12-08T15:27:46Z |
A 1.5 v CMOS current-mode cyclic analog-to-digital converter with digital error correction
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CHEN, CC; WU, CY; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:27:44Z |
Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's
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Ker, MD; Wu, CY; Cheng, T; Chang, HH; Wu, MJN; Yu, TL |
| 國立交通大學 |
2014-12-08T15:27:39Z |
Dual-mode Viterbi decoder design for cellular mobile
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Chen, AY; Wu, CY; Wen, KA |
| 國立交通大學 |
2014-12-08T15:27:38Z |
Pulse-width-modulation feedforward neural network design with on-chip learning
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Bor, JC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:38Z |
CMOS rotation-invariant pattern recognition system
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Chiu, CF; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:38Z |
Bipolar bootstrapped multi-emitter BiCMOS ((BM)-M-2-BiCMOS) logic for low-voltage applications
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Wu, CY; Tseng, YK |
| 國立交通大學 |
2014-12-08T15:27:34Z |
A new CMOS readout circuit design for the IR FPA with adaptive gain control and current-mode background suppression
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Hsieh, CC; Wu, CY; Jih, FW; Sun, TP; Chang, H |
| 國立交通大學 |
2014-12-08T15:27:34Z |
The CMOS design of robust neural chip with the on-chip learning capability
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Wu, CY; Liu, RY; Jou, IC; ShyhJYE, FJ |
| 國立交通大學 |
2014-12-08T15:27:27Z |
The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification
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Lan, JF; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:27Z |
A 1.5V differential cross-coupled bootstrapped BiCMOS logic
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Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:23Z |
A 1.2 V CMOS four-quadrant analog multiplier
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Hsiao, SY; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:18Z |
A new true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logic
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Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:18Z |
The BJT-based silicon-retina sensory system for direction- and velocity-selective sensing
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Jiang, HC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:18Z |
A 1.8GHz CMOS quadrature voltage-controlled oscillator (VCO) using the constant-current LC ring oscillator structure
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Wu, CY; Kao, HS |
| 國立交通大學 |
2014-12-08T15:27:17Z |
Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology
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Ker, MD; Chen, TY; Wu, CY; Tang, H; Su, KC; Sun, SW |
| 國立交通大學 |
2014-12-08T15:27:12Z |
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS
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Wu, CY; Yu-Yee, L |
| 國立交通大學 |
2014-12-08T15:27:12Z |
The design of high-performance 128Xi28 CMOS image sensors using new current-readout techniques
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Shih, YC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:12Z |
A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level
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Yen, WC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:06Z |
A low-power 1.2GHz 0.35um CMOS PLL
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Juang, DC; Chen, DS; Shyu, JM; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:05Z |
A compact CMOS 2V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9GHz RF transmitter applications
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Kao, HS; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:05Z |
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications
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Ker, MD; Chen, TY; Wu, CY; Chang, HH |
| 國立交通大學 |
2014-12-08T15:27:05Z |
The design of cellular neural network with ratio memory for pattern learning and recognition
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Wu, CY; Cheng, CH |
显示项目 206-230 / 607 (共25页)
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