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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"wu cy"的相关文件
显示项目 211-220 / 607 (共61页)
<< < 17 18 19 20 21 22 23 24 25 26 > >>
每页显示[10|25|50]项目
| 國立交通大學 |
2014-12-08T15:27:39Z |
Dual-mode Viterbi decoder design for cellular mobile
|
Chen, AY; Wu, CY; Wen, KA |
| 國立交通大學 |
2014-12-08T15:27:38Z |
Pulse-width-modulation feedforward neural network design with on-chip learning
|
Bor, JC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:38Z |
CMOS rotation-invariant pattern recognition system
|
Chiu, CF; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:38Z |
Bipolar bootstrapped multi-emitter BiCMOS ((BM)-M-2-BiCMOS) logic for low-voltage applications
|
Wu, CY; Tseng, YK |
| 國立交通大學 |
2014-12-08T15:27:34Z |
A new CMOS readout circuit design for the IR FPA with adaptive gain control and current-mode background suppression
|
Hsieh, CC; Wu, CY; Jih, FW; Sun, TP; Chang, H |
| 國立交通大學 |
2014-12-08T15:27:34Z |
The CMOS design of robust neural chip with the on-chip learning capability
|
Wu, CY; Liu, RY; Jou, IC; ShyhJYE, FJ |
| 國立交通大學 |
2014-12-08T15:27:27Z |
The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification
|
Lan, JF; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:27Z |
A 1.5V differential cross-coupled bootstrapped BiCMOS logic
|
Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:23Z |
A 1.2 V CMOS four-quadrant analog multiplier
|
Hsiao, SY; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:18Z |
A new true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logic
|
Tseng, YK; Wu, CY |
显示项目 211-220 / 607 (共61页)
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每页显示[10|25|50]项目
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