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"wu cy"的相關文件
顯示項目 196-220 / 607 (共25頁)
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| 國立交通大學 |
2014-12-08T15:27:55Z |
AN ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER WITH LOW RATIO-SENSITIVITY AND GAIN-SENSITIVITY AND 4N-CLOCK CONVERSION CYCLE
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CHIN, SY; WU, CY |
| 國立交通大學 |
2014-12-08T15:27:55Z |
THE DESIGN OF THE CMOS CURRENT-MODE GENERAL-PURPOSE ANALOG PROCESSOR
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LU, LH; WU, CY |
| 國立交通大學 |
2014-12-08T15:27:55Z |
VHF UHF HIGH-Q BANDPASS TUNABLE FILTERS DESIGN USING CMOS INVERTER-BASED TRANSRESISTANCE AMPLIFIERS
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LU, PH; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:27:55Z |
THE CONTINUOUS-TIME VHF LOWPASS FILTER DESIGN USING FINITE-GAIN CURRENT AND VOLTAGE AMPLIFIERS AND SPECIAL Q-ENHANCEMENT CIRCUITS
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WU, CY; HSU, HS |
| 國立交通大學 |
2014-12-08T15:27:53Z |
AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS
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KER, MD; WU, CY; JIANG, HC; LEE, CY; KO, J; HSUE, P |
| 國立交通大學 |
2014-12-08T15:27:51Z |
A NEW SWITCH-CURRENT INTEGRATION READOUT STRUCTURE FOR INFRARED FOCAL PLANE ARRAY
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HSIEH, CC; WU, CY; JIH, FW; SUN, TP; YANG, SJ |
| 國立交通大學 |
2014-12-08T15:27:50Z |
A NEW CMOS PROGRAMMABLE GAIN CONTROLLER WITH A WIDE DYNAMIC RANGE
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KANG, R; YU, TC; WU, CY |
| 國立交通大學 |
2014-12-08T15:27:47Z |
Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's
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KER, MD; WU, CY; CHANG, HH; CHENG, T; WU, TS |
| 國立交通大學 |
2014-12-08T15:27:47Z |
A 1.5 V CMOS balanced differential switched-capacitor filter with internal clock boosters
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WU, CY; WEY, WS; YU, TC |
| 國立交通大學 |
2014-12-08T15:27:47Z |
CMOS current-mode outstar neural networks with long-period analog ratio memory
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LAU, JF; WU, CY |
| 國立交通大學 |
2014-12-08T15:27:47Z |
A 3-V 1-GHz low-noise bandpass amplifier
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WU, CY; HSIAO, SY; LIU, RY |
| 國立交通大學 |
2014-12-08T15:27:46Z |
A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
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WU, CY; CHENG, KH; LU, JH |
| 國立交通大學 |
2014-12-08T15:27:46Z |
The design of new low-voltage CMOS VHF continuous-time lowpass biquad filters
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WU, CY; HSU, HS |
| 國立交通大學 |
2014-12-08T15:27:46Z |
A 1.5 v CMOS current-mode cyclic analog-to-digital converter with digital error correction
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CHEN, CC; WU, CY; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:27:44Z |
Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's
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Ker, MD; Wu, CY; Cheng, T; Chang, HH; Wu, MJN; Yu, TL |
| 國立交通大學 |
2014-12-08T15:27:39Z |
Dual-mode Viterbi decoder design for cellular mobile
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Chen, AY; Wu, CY; Wen, KA |
| 國立交通大學 |
2014-12-08T15:27:38Z |
Pulse-width-modulation feedforward neural network design with on-chip learning
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Bor, JC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:38Z |
CMOS rotation-invariant pattern recognition system
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Chiu, CF; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:38Z |
Bipolar bootstrapped multi-emitter BiCMOS ((BM)-M-2-BiCMOS) logic for low-voltage applications
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Wu, CY; Tseng, YK |
| 國立交通大學 |
2014-12-08T15:27:34Z |
A new CMOS readout circuit design for the IR FPA with adaptive gain control and current-mode background suppression
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Hsieh, CC; Wu, CY; Jih, FW; Sun, TP; Chang, H |
| 國立交通大學 |
2014-12-08T15:27:34Z |
The CMOS design of robust neural chip with the on-chip learning capability
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Wu, CY; Liu, RY; Jou, IC; ShyhJYE, FJ |
| 國立交通大學 |
2014-12-08T15:27:27Z |
The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification
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Lan, JF; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:27Z |
A 1.5V differential cross-coupled bootstrapped BiCMOS logic
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Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:23Z |
A 1.2 V CMOS four-quadrant analog multiplier
|
Hsiao, SY; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:18Z |
A new true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logic
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Tseng, YK; Wu, CY |
顯示項目 196-220 / 607 (共25頁)
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