English  |  正體中文  |  简体中文  |  總筆數 :0  
造訪人次 :  51827542    線上人數 :  794
教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
關於TAIR

瀏覽

消息

著作權

相關連結

"wu cy"的相關文件

回到依作者瀏覽
依題名排序 依日期排序

顯示項目 296-320 / 607 (共25頁)
<< < 7 8 9 10 11 12 13 14 15 16 > >>
每頁顯示[10|25|50]項目

機構 日期 題名 作者
國立交通大學 2014-12-08T15:06:15Z A SIMPLE PUNCHTHROUGH VOLTAGE MODEL FOR SHORT-CHANNEL MOSFETS WITH SINGLE CHANNEL IMPLANTATION IN VLSI WU, CY; HSIAO, WZ; CHEN, HH
國立交通大學 2014-12-08T15:06:15Z A NEW METHOD FOR COMPUTER-AIDED OPTIMIZATION OF SOLAR-CELL STRUCTURES CHEN, MJ; WU, CY
國立交通大學 2014-12-08T15:06:15Z A STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTION CHEN, MJ; WU, CY
國立交通大學 2014-12-08T15:06:13Z THE LAMBDA-BIPOLAR PHOTOTRANSISTOR ANALYSIS AND APPLICATIONS WU, CY; SHENG, HD; TSAI, YT
國立交通大學 2014-12-08T15:06:13Z AN ACCURATE AND ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY MOSFETS WITH SINGLE-CHANNEL ION-IMPLANTATION IN VLSI WU, CY; HUANG, GS; CHEN, HH; TSENG, FC; SHIH, CT
國立交通大學 2014-12-08T15:06:13Z AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATION WU, CY; DAIH, YW
國立交通大學 2014-12-08T15:06:13Z A NEW THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY BURIED-CHANNEL MOSFETS WU, CY; HSU, KC
國立交通大學 2014-12-08T15:06:13Z MOBILITY MODELS FOR THE IV CHARACTERISTICS OF BURIED-CHANNEL MOSFETS WU, CY; HSU, KC
國立交通大學 2014-12-08T15:06:12Z SUPERIOR CHARACTERISTICS OF NITRIDIZED THERMAL OXIDE GROWN ON POLYCRYSTALLINE SILICON CHEN, CF; WU, CY
國立交通大學 2014-12-08T15:06:11Z AN EFFICIENT METHOD FOR CALCULATING THE DC TRIGGERING CURRENTS IN CMOS LATCH-UP CHEN, MJ; WU, CY
國立交通大學 2014-12-08T15:06:11Z A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES CHEN, MJ; WU, CY
國立交通大學 2014-12-08T15:06:11Z AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATION WU, CY; HUANG, GS; CHEN, HH
國立交通大學 2014-12-08T15:06:11Z AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS CHEN, MJ; WU, CY
國立交通大學 2014-12-08T15:06:09Z AN ENVIRONMENT-INSENSITIVE TRILAYER STRUCTURE FOR TITANIUM SILICIDE FORMATION LIN, MZ; YU, YCS; WU, CY
國立交通大學 2014-12-08T15:06:09Z A CHARACTERIZATION MODEL FOR RAMP-VOLTAGE-STRESSED IV CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE CHEN, CF; WU, CY
國立交通大學 2014-12-08T15:06:09Z CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERS CHEN, MJ; WU, CY
國立交通大學 2014-12-08T15:06:08Z A NEW OXIDATION-RESISTANT SELF-ALIGNED TISI2 PROCESS TSENG, HH; WU, CY
國立交通大學 2014-12-08T15:06:07Z A CHARACTERIZATION MODEL FOR CONSTANT CURRENT STRESSED VOLTAGE-TIME CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE CHEN, CF; WU, CY
國立交通大學 2014-12-08T15:06:06Z THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC WU, CY; WANG, JS; TSAI, MK
國立交通大學 2014-12-08T15:06:06Z A SIMPLE TECHNIQUE FOR MEASURING THE INTERFACE-STATE DENSITY OF THE SCHOTTKY-BARRIER DIODES USING THE CURRENT-VOLTAGE CHARACTERISTICS TSENG, HH; WU, CY
國立交通大學 2014-12-08T15:06:05Z THE DISTORTION OF THE INTERFACE-STATE SPECTRUM DUE TO NONEQUILIBRIUM OCCUPANCY OF THE INTERFACE STATES AT THE METAL-SEMICONDUCTOR INTERFACE TSENG, HH; WU, CY
國立交通大學 2014-12-08T15:06:05Z THE EFFECTS OF THERMAL NITRIDATION CONDITIONS ON THE RELIABILITY OF THIN NITRIDED OXIDE-FILMS TSAI, HH; WU, LC; WU, CY; HU, CM
國立交通大學 2014-12-08T15:06:05Z A NEW STRUCTURE-ORIENTED MODEL FOR WELL RESISTANCE IN CMOS LATCHUP STRUCTURES CHEN, MJ; SZE, SC; CHEN, HH; WU, CY
國立交通大學 2014-12-08T15:06:05Z A SIMPLE INTERFACIAL-LAYER MODEL FOR THE NONIDEAL IV AND C-V CHARACTERISTICS OF THE SCHOTTKY-BARRIER DIODE TSENG, HH; WU, CY
國立交通大學 2014-12-08T15:06:04Z AN ANALYTIC IV MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICES HUANG, GS; WU, CY

顯示項目 296-320 / 607 (共25頁)
<< < 7 8 9 10 11 12 13 14 15 16 > >>
每頁顯示[10|25|50]項目