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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"wu cy"的相關文件
顯示項目 306-315 / 607 (共61頁)
<< < 26 27 28 29 30 31 32 33 34 35 > >>
每頁顯示[10|25|50]項目
| 國立交通大學 |
2014-12-08T15:06:11Z |
A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES
|
CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATION
|
WU, CY; HUANG, GS; CHEN, HH |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS
|
CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
AN ENVIRONMENT-INSENSITIVE TRILAYER STRUCTURE FOR TITANIUM SILICIDE FORMATION
|
LIN, MZ; YU, YCS; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
A CHARACTERIZATION MODEL FOR RAMP-VOLTAGE-STRESSED IV CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE
|
CHEN, CF; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERS
|
CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:08Z |
A NEW OXIDATION-RESISTANT SELF-ALIGNED TISI2 PROCESS
|
TSENG, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:07Z |
A CHARACTERIZATION MODEL FOR CONSTANT CURRENT STRESSED VOLTAGE-TIME CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE
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CHEN, CF; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:06Z |
THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC
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WU, CY; WANG, JS; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:06:06Z |
A SIMPLE TECHNIQUE FOR MEASURING THE INTERFACE-STATE DENSITY OF THE SCHOTTKY-BARRIER DIODES USING THE CURRENT-VOLTAGE CHARACTERISTICS
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TSENG, HH; WU, CY |
顯示項目 306-315 / 607 (共61頁)
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每頁顯示[10|25|50]項目
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