臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

關於TAIR
	計畫說明

瀏覽
	典藏機構
	作者
	題名
	日期
	統計圖表
	機構即時統計
	學術趨勢

消息
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

著作權
	出版社及期刊政策查詢
	TAIR著作權會議記錄

相關連結
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"wu cy"的相關文件

回到依作者瀏覽
依題名排序	依日期排序

顯示項目 326-375 / 607 (共13頁)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
每頁顯示[10|25|50]項目

機構	日期	題名	作者
國立交通大學	2014-12-08T15:06:01Z	THE EFFECTS OF THERMAL SILICIDATION ON THE CURRENT TRANSPORT CHARACTERISTICS OF TI/(111)SI SCHOTTKY-BARRIER CONTACTS	TSENG, HH; WU, CY
國立交通大學	2014-12-08T15:06:00Z	A NEW METHOD FOR DETERMINING THE TERMINAL SERIES RESISTANCES AND HIGH-INJECTION COEFFICIENT OF BIPOLAR-TRANSISTORS IN CMOS INTEGRATED-CIRCUITS FOR COMPUTER-AIDED CIRCUIT MODELING	YANG, YH; WU, CY; CHEN, WY
國立交通大學	2014-12-08T15:06:00Z	GENERAL EXPERIMENTAL-METHOD OF PARAMETER EXTRACTION FOR CMOS TIMING MACROMODELS	WU, CY; JANG, WY; WU, HJ
國立交通大學	2014-12-08T15:05:59Z	INTEGRAL-EQUATION SOLUTION FOR HYPERBOLIC HEAT-CONDUCTION WITH SURFACE RADIATION	WU, CY
國立交通大學	2014-12-08T15:05:59Z	TIMING MACROMODELS FOR CMOS STATIC SET RESET LATCHES AND THEIR APPLICATIONS	WU, CY; LI, C; HWANG, JS
國立交通大學	2014-12-08T15:05:57Z	A NEW EXPERIMENTAL-METHOD TO DETERMINE THE SATURATION VOLTAGE OF A SMALL-GEOMETRY MOSFET	JANG, WY; WU, CY; WU, HJ
國立交通大學	2014-12-08T15:05:57Z	A NEW LATERAL GROWTH FREE FORMATION TECHNIQUE FOR TITANIUM SILICIDE USING THE SI/W/TI TRILAYER STRUCTURE	LIN, MZ; WU, CY
國立交通大學	2014-12-08T15:05:56Z	LOW-POWER DYNAMIC TERNARY LOGIC	WANG, JS; WU, CY; TSAI, MK
國立交通大學	2014-12-08T15:05:55Z	COBALT SILICIDE INTERCONNECTION FROM A SI/W/CO TRILAYER STRUCTURE	LIN, MZ; WU, CY
國立交通大學	2014-12-08T15:05:53Z	NEW MONOLITHIC SWITCHED-CAPACITOR DIFFERENTIATORS WITH GOOD NOISE REJECTION	WU, CY; YU, TC; CHANG, SS
國立交通大學	2014-12-08T15:05:51Z	THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS	YANG, YH; WU, CY
國立交通大學	2014-12-08T15:05:50Z	NOVEL DYNAMIC CMOS LOGIC FREE FROM PROBLEMS OF CHARGE SHARING AND CLOCK SKEW	WANG, JS; WU, CY; TSAI, MK
國立交通大學	2014-12-08T15:05:49Z	AN IMPROVED PROPAGATION-DELAY-TIME FORMULA FOR THE SUB-MICRON N-MOS INVERTER	WU, CY
國立交通大學	2014-12-08T15:05:48Z	A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS	YANG, YH; WU, CY
國立交通大學	2014-12-08T15:05:48Z	A NEW TWIN-WELL CMOS PROCESS USING NITRIDIZED-OXIDE-LOCOS (NOLOCOS) ISOLATION TECHNOLOGY	TSAI, HH; YU, CL; WU, CY
國立交通大學	2014-12-08T15:05:48Z	PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS	WU, CY; HWANG, JS
國立交通大學	2014-12-08T15:05:48Z	CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS	WANG, JS; WU, CY; TSAI, MK
國立交通大學	2014-12-08T15:05:45Z	ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES	YANG, YH; WU, CY
國立交通大學	2014-12-08T15:05:45Z	A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC	WU, CY; LIN, YT
國立交通大學	2014-12-08T15:05:40Z	REALIZATIONS OF IIR FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE	YU, TC; WU, CY; CHANG, SS
國立交通大學	2014-12-08T15:05:39Z	A NEW ALGORITHM FOR STEADY-STATE 2-D NUMERICAL-SIMULATION OF MOSFETS	PERNG, RK; WU, CY
國立交通大學	2014-12-08T15:05:37Z	THE SIGNAL DELAY IN INTERCONNECTION LINES CONSIDERING THE EFFECTS OF SMALL-GEOMETRY CMOS INVERTERS	SHIAU, MC; WU, CY
國立交通大學	2014-12-08T15:05:37Z	A QUASI-2-DIMENSIONAL ANALYTICAL MODEL FOR THE TURN-ON CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORS	LIN, PS; GUO, JY; WU, CY
國立交通大學	2014-12-08T15:05:37Z	THE EFFECT OF GATE ELECTRODES USING TUNGSTEN SILICIDES AND OR POLYSILICON ON THE DIELECTRIC CHARACTERISTICS OF VERY THIN OXIDES	CHENG, HC; CHAO, CY; SU, WD; CHANG, SW; LEE, MK; WU, CY
國立交通大學	2014-12-08T15:05:35Z	MOS DEVICE PARAMETER OPTIMIZATION BASED ON TRANSIENT TRAJECTORY CONSIDERATIONS	WU, CY; JANG, WY; LIU, ID
國立交通大學	2014-12-08T15:05:32Z	AN ANALYTIC SATURATION MODEL FOR DRAIN AND SUBSTRATE CURRENTS OF CONVENTIONAL AND LDD MOSFETS	HUANG, GS; WU, CY
國立交通大學	2014-12-08T15:05:32Z	EXCELLENT THERMAL-STABILITY OF COBALT ALUMINUM-ALLOY SCHOTTKY CONTACTS ON GAAS SUBSTRATES	CHENG, HC; WU, CY; SHY, JJ
國立交通大學	2014-12-08T15:05:30Z	EFFICIENT PHYSICAL TIMING MODELS FOR CMOS AND-OR-INVERTER AND OR-AND-INVERTER GATES AND THEIR APPLICATIONS	WU, CY; SHIAU, MC
國立交通大學	2014-12-08T15:05:27Z	REALIZATIONS OF IIR/FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE	YU, TC; WU, CY; CHANG, SC
國立交通大學	2014-12-08T15:05:27Z	DELAY MODELS AND SPEED IMPROVEMENT TECHNIQUES FOR RC TREE INTERCONNECTIONS AMONG SMALL-GEOMETRY CMOS INVERTERS	WU, CY; SHIAU, MC
國立交通大學	2014-12-08T15:05:25Z	PHYSICAL TIMING MODELS AND DESIGN METHODOLOGY OF BIPOLAR NONTHRESHOLD LOGIC-CIRCUITS	WU, CY; WU, TS
國立交通大學	2014-12-08T15:05:17Z	NEW PHYSICAL TIMING MODELS OF BIPOLAR NONSATURATION LOGIC USING CURRENT DOMAIN ANALYSIS TECHNIQUE	WU, CY; WU, TS
國立交通大學	2014-12-08T15:05:15Z	EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS	HWANG, JS; WU, CY
國立交通大學	2014-12-08T15:05:14Z	A NEW METHODOLOGY FOR DEVELOPING A FAST 2-DIMENSIONAL MOSFET DEVICE SIMULATOR	PERNG, RK; LIN, PS; WU, CY
國立交通大學	2014-12-08T15:05:13Z	A NEW SIMPLIFIED 2-DIMENSIONAL MODEL FOR THE THRESHOLD VOLTAGE OF MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE	LIN, PS; WU, CY
國立交通大學	2014-12-08T15:05:10Z	LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI	WU, CY; CHENG, KH
國立交通大學	2014-12-08T15:05:08Z	DESIGN TECHNIQUES FOR HIGH-FREQUENCY CMOS SWITCHED-CAPACITOR FILTERS USING NON-OP-AMP-BASED UNITY-GAIN AMPLIFIERS	WU, CY; LU, PH; TSAI, MK
國立交通大學	2014-12-08T15:04:59Z	A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI	WU, CY; KER, MD; LEE, CY; KO, J
國立交通大學	2014-12-08T15:04:54Z	PHYSICAL MODEL FOR CHARACTERIZING AND SIMULATING A FLOTOX EEPROM DEVICE	WU, CY; CHEN, CF
國立交通大學	2014-12-08T15:04:49Z	THE PROCESS WINDOW OF A-SI/TI BILAYER METALLIZATION FOR AN OXIDATION-RESISTANT AND SELF-ALIGNED TISI2 PROCESS	LOU, YS; WU, CY; CHENG, HC
國立交通大學	2014-12-08T15:04:49Z	A NEW 2-DIMENSIONAL MODEL FOR THE POTENTIAL DISTRIBUTION OF SHORT GATE-LENGTH MESFETS AND ITS APPLICATIONS	CHIN, SP; WU, CY
國立交通大學	2014-12-08T15:04:48Z	HIGH-PRECISION CURVATURE-COMPENSATED CMOS BAND-GAP VOLTAGE AND CURRENT REFERENCES	WU, CY; CHIN, SY
國立交通大學	2014-12-08T15:04:48Z	NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONS	HWANG, JS; WU, CY
國立交通大學	2014-12-08T15:04:43Z	A NEW METHODOLOGY FOR 2-DIMENSIONAL NUMERICAL-SIMULATION OF SEMICONDUCTOR-DEVICES	CHIN, SP; WU, CY
國立交通大學	2014-12-08T15:04:41Z	ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGIC	WU, CY; CHENG, KH; WANG, JS
國立交通大學	2014-12-08T15:04:41Z	A NEW OXIDATION-RESISTANT COSI2 PROCESS FOR SELF-ALIGNED SILICIDATION (SALICIDE) TECHNOLOGY	LOU, YS; WU, CY; CHENG, HC
國立交通大學	2014-12-08T15:04:34Z	A NEW IV MODEL FOR SHORT GATE-LENGTH MESFETS	CHIN, SP; WU, CY
國立交通大學	2014-12-08T15:04:25Z	DESIGN AND APPLICATION OF PIPELINED DYNAMIC CMOS TERNARY LOGIC AND SIMPLE TERNARY DIFFERENTIAL LOGIC	WU, CY; HUANG, HY
國立交通大學	2014-12-08T15:04:23Z	A NEW GRID-GENERATION METHOD FOR 2-D SIMULATION OF DEVICES WITH NONPLANAR SEMICONDUCTOR SURFACE	CHIN, SP; WU, CY
國立交通大學	2014-12-08T15:04:22Z	A NEW 2D ANALYTIC THRESHOLD-VOLTAGE MODEL FOR FULLY DEPLETED SHORT-CHANNEL SOI MOSFETS	GUO, JY; WU, CY

顯示項目 326-375 / 607 (共13頁)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
每頁顯示[10|25|50]項目

	English \| 正體中文 \| 简体中文 \| 總筆數 :0
	造訪人次 : 51824944 線上人數 : 779 教育部委託研究計畫計畫執行:國立臺灣大學圖書館