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"wu cy"的相關文件
顯示項目 336-360 / 607 (共25頁)
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| 國立交通大學 |
2014-12-08T15:05:51Z |
THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:50Z |
NOVEL DYNAMIC CMOS LOGIC FREE FROM PROBLEMS OF CHARGE SHARING AND CLOCK SKEW
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:49Z |
AN IMPROVED PROPAGATION-DELAY-TIME FORMULA FOR THE SUB-MICRON N-MOS INVERTER
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WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
A NEW TWIN-WELL CMOS PROCESS USING NITRIDIZED-OXIDE-LOCOS (NOLOCOS) ISOLATION TECHNOLOGY
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TSAI, HH; YU, CL; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS
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WU, CY; HWANG, JS |
| 國立交通大學 |
2014-12-08T15:05:48Z |
CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:45Z |
ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:45Z |
A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC
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WU, CY; LIN, YT |
| 國立交通大學 |
2014-12-08T15:05:40Z |
REALIZATIONS OF IIR FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE
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YU, TC; WU, CY; CHANG, SS |
| 國立交通大學 |
2014-12-08T15:05:39Z |
A NEW ALGORITHM FOR STEADY-STATE 2-D NUMERICAL-SIMULATION OF MOSFETS
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PERNG, RK; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:37Z |
THE SIGNAL DELAY IN INTERCONNECTION LINES CONSIDERING THE EFFECTS OF SMALL-GEOMETRY CMOS INVERTERS
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SHIAU, MC; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:37Z |
A QUASI-2-DIMENSIONAL ANALYTICAL MODEL FOR THE TURN-ON CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORS
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LIN, PS; GUO, JY; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:37Z |
THE EFFECT OF GATE ELECTRODES USING TUNGSTEN SILICIDES AND OR POLYSILICON ON THE DIELECTRIC CHARACTERISTICS OF VERY THIN OXIDES
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CHENG, HC; CHAO, CY; SU, WD; CHANG, SW; LEE, MK; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:35Z |
MOS DEVICE PARAMETER OPTIMIZATION BASED ON TRANSIENT TRAJECTORY CONSIDERATIONS
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WU, CY; JANG, WY; LIU, ID |
| 國立交通大學 |
2014-12-08T15:05:32Z |
AN ANALYTIC SATURATION MODEL FOR DRAIN AND SUBSTRATE CURRENTS OF CONVENTIONAL AND LDD MOSFETS
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HUANG, GS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:32Z |
EXCELLENT THERMAL-STABILITY OF COBALT ALUMINUM-ALLOY SCHOTTKY CONTACTS ON GAAS SUBSTRATES
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CHENG, HC; WU, CY; SHY, JJ |
| 國立交通大學 |
2014-12-08T15:05:30Z |
EFFICIENT PHYSICAL TIMING MODELS FOR CMOS AND-OR-INVERTER AND OR-AND-INVERTER GATES AND THEIR APPLICATIONS
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WU, CY; SHIAU, MC |
| 國立交通大學 |
2014-12-08T15:05:27Z |
REALIZATIONS OF IIR/FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE
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YU, TC; WU, CY; CHANG, SC |
| 國立交通大學 |
2014-12-08T15:05:27Z |
DELAY MODELS AND SPEED IMPROVEMENT TECHNIQUES FOR RC TREE INTERCONNECTIONS AMONG SMALL-GEOMETRY CMOS INVERTERS
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WU, CY; SHIAU, MC |
| 國立交通大學 |
2014-12-08T15:05:25Z |
PHYSICAL TIMING MODELS AND DESIGN METHODOLOGY OF BIPOLAR NONTHRESHOLD LOGIC-CIRCUITS
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WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:17Z |
NEW PHYSICAL TIMING MODELS OF BIPOLAR NONSATURATION LOGIC USING CURRENT DOMAIN ANALYSIS TECHNIQUE
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WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:15Z |
EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS
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HWANG, JS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:14Z |
A NEW METHODOLOGY FOR DEVELOPING A FAST 2-DIMENSIONAL MOSFET DEVICE SIMULATOR
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PERNG, RK; LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:13Z |
A NEW SIMPLIFIED 2-DIMENSIONAL MODEL FOR THE THRESHOLD VOLTAGE OF MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE
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LIN, PS; WU, CY |
顯示項目 336-360 / 607 (共25頁)
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