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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"wu cy"的相關文件
顯示項目 356-365 / 607 (共61頁)
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每頁顯示[10|25|50]項目
| 國立交通大學 |
2014-12-08T15:05:25Z |
PHYSICAL TIMING MODELS AND DESIGN METHODOLOGY OF BIPOLAR NONTHRESHOLD LOGIC-CIRCUITS
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WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:17Z |
NEW PHYSICAL TIMING MODELS OF BIPOLAR NONSATURATION LOGIC USING CURRENT DOMAIN ANALYSIS TECHNIQUE
|
WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:15Z |
EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS
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HWANG, JS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:14Z |
A NEW METHODOLOGY FOR DEVELOPING A FAST 2-DIMENSIONAL MOSFET DEVICE SIMULATOR
|
PERNG, RK; LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:13Z |
A NEW SIMPLIFIED 2-DIMENSIONAL MODEL FOR THE THRESHOLD VOLTAGE OF MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE
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LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:10Z |
LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI
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WU, CY; CHENG, KH |
| 國立交通大學 |
2014-12-08T15:05:08Z |
DESIGN TECHNIQUES FOR HIGH-FREQUENCY CMOS SWITCHED-CAPACITOR FILTERS USING NON-OP-AMP-BASED UNITY-GAIN AMPLIFIERS
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WU, CY; LU, PH; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:04:59Z |
A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
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WU, CY; KER, MD; LEE, CY; KO, J |
| 國立交通大學 |
2014-12-08T15:04:54Z |
PHYSICAL MODEL FOR CHARACTERIZING AND SIMULATING A FLOTOX EEPROM DEVICE
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WU, CY; CHEN, CF |
| 國立交通大學 |
2014-12-08T15:04:49Z |
THE PROCESS WINDOW OF A-SI/TI BILAYER METALLIZATION FOR AN OXIDATION-RESISTANT AND SELF-ALIGNED TISI2 PROCESS
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LOU, YS; WU, CY; CHENG, HC |
顯示項目 356-365 / 607 (共61頁)
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每頁顯示[10|25|50]項目
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