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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"wu cy"的相關文件
顯示項目 391-400 / 607 (共61頁)
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每頁顯示[10|25|50]項目
| 國立交通大學 |
2014-12-08T15:03:36Z |
PRECISE CMOS CURRENT SAMPLE HOLD CIRCUITS USING DIFFERENTIAL CLOCK FEEDTHROUGH ATTENUATION TECHNIQUES
|
WU, CY; CHEN, CC; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:03:30Z |
LATERAL TITANIUM SILICIDE GROWTH AND ITS SUPPRESSION USING THE A-SI/TI BILAYER STRUCTURE
|
LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:27Z |
A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION
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WEN, KS; LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:25Z |
A NOVEL EXTRACTION TECHNIQUE FOR THE EFFECTIVE CHANNEL-LENGTH OF MOSFET DEVICES
|
LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:24Z |
A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES
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WU, CY; CHEN, CC; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:03:22Z |
CMOS CURRENT-MODE IMPLEMENTATION OF SPATIOTEMPORAL PROBABILISTIC NEURAL NETWORKS FOR SPEECH RECOGNITION
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WU, CY; LIU, RY; JOU, IC |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:17Z |
A NEW CONSTANT-FIELD SCALING THEORY FOR MOSFETS
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MAA, JJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:16Z |
COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS
|
KER, MD; WU, CY |
顯示項目 391-400 / 607 (共61頁)
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每頁顯示[10|25|50]項目
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