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"wu cy"
Showing items 301-310 of 607 (61 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:06:13Z |
AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATION
|
WU, CY; DAIH, YW |
| 國立交通大學 |
2014-12-08T15:06:13Z |
A NEW THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY BURIED-CHANNEL MOSFETS
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WU, CY; HSU, KC |
| 國立交通大學 |
2014-12-08T15:06:13Z |
MOBILITY MODELS FOR THE IV CHARACTERISTICS OF BURIED-CHANNEL MOSFETS
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WU, CY; HSU, KC |
| 國立交通大學 |
2014-12-08T15:06:12Z |
SUPERIOR CHARACTERISTICS OF NITRIDIZED THERMAL OXIDE GROWN ON POLYCRYSTALLINE SILICON
|
CHEN, CF; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN EFFICIENT METHOD FOR CALCULATING THE DC TRIGGERING CURRENTS IN CMOS LATCH-UP
|
CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:11Z |
A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES
|
CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATION
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WU, CY; HUANG, GS; CHEN, HH |
| 國立交通大學 |
2014-12-08T15:06:11Z |
AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS
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CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
AN ENVIRONMENT-INSENSITIVE TRILAYER STRUCTURE FOR TITANIUM SILICIDE FORMATION
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LIN, MZ; YU, YCS; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
A CHARACTERIZATION MODEL FOR RAMP-VOLTAGE-STRESSED IV CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE
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CHEN, CF; WU, CY |
Showing items 301-310 of 607 (61 Page(s) Totally)
<< < 26 27 28 29 30 31 32 33 34 35 > >>
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