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Taiwan Academic Institutional Repository >
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"wu cy"
Showing items 321-345 of 607 (25 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:06:04Z |
SUPERIOR CHARACTERISTICS OF THERMAL OXIDE LAYERS GROWN ON AMORPHOUS-SILICON FILMS
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WU, CY; CHEN, CF |
| 國立交通大學 |
2014-12-08T15:06:03Z |
A NEW APPROACH TO ANALYTICALLY SOLVING THE TWO-DIMENSIONAL POISSON EQUATION AND ITS APPLICATION IN SHORT-CHANNEL MOSFET MODELING
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LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:03Z |
A SIMPLIFIED COMPUTER-ANALYSIS FOR NORMAL-WELL GUARD RING EFFICIENCY IN CMOS CIRCUITS
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CHEN, MJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:03Z |
THE DIELECTRIC RELIABILITY OF INTRINSIC THIN SIO2-FILMS THERMALLY GROWN ON A HEAVILY DOPED SI SUBSTRATE - CHARACTERIZATION AND MODELING
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CHEN, CF; WU, CY; LEE, MK; CHEN, CN |
| 國立交通大學 |
2014-12-08T15:06:03Z |
TRANSPORT-PROPERTIES OF THERMAL OXIDE-FILMS GROWN ON POLYCRYSTALLINE SILICON - MODELING AND EXPERIMENTS
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WU, CY; CHEN, CF |
| 國立交通大學 |
2014-12-08T15:06:01Z |
THE EFFECTS OF THERMAL SILICIDATION ON THE CURRENT TRANSPORT CHARACTERISTICS OF TI/(111)SI SCHOTTKY-BARRIER CONTACTS
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TSENG, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:00Z |
A NEW METHOD FOR DETERMINING THE TERMINAL SERIES RESISTANCES AND HIGH-INJECTION COEFFICIENT OF BIPOLAR-TRANSISTORS IN CMOS INTEGRATED-CIRCUITS FOR COMPUTER-AIDED CIRCUIT MODELING
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YANG, YH; WU, CY; CHEN, WY |
| 國立交通大學 |
2014-12-08T15:06:00Z |
GENERAL EXPERIMENTAL-METHOD OF PARAMETER EXTRACTION FOR CMOS TIMING MACROMODELS
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WU, CY; JANG, WY; WU, HJ |
| 國立交通大學 |
2014-12-08T15:05:59Z |
INTEGRAL-EQUATION SOLUTION FOR HYPERBOLIC HEAT-CONDUCTION WITH SURFACE RADIATION
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WU, CY |
| 國立交通大學 |
2014-12-08T15:05:59Z |
TIMING MACROMODELS FOR CMOS STATIC SET RESET LATCHES AND THEIR APPLICATIONS
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WU, CY; LI, C; HWANG, JS |
| 國立交通大學 |
2014-12-08T15:05:57Z |
A NEW EXPERIMENTAL-METHOD TO DETERMINE THE SATURATION VOLTAGE OF A SMALL-GEOMETRY MOSFET
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JANG, WY; WU, CY; WU, HJ |
| 國立交通大學 |
2014-12-08T15:05:57Z |
A NEW LATERAL GROWTH FREE FORMATION TECHNIQUE FOR TITANIUM SILICIDE USING THE SI/W/TI TRILAYER STRUCTURE
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LIN, MZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:56Z |
LOW-POWER DYNAMIC TERNARY LOGIC
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:55Z |
COBALT SILICIDE INTERCONNECTION FROM A SI/W/CO TRILAYER STRUCTURE
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LIN, MZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:53Z |
NEW MONOLITHIC SWITCHED-CAPACITOR DIFFERENTIATORS WITH GOOD NOISE REJECTION
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WU, CY; YU, TC; CHANG, SS |
| 國立交通大學 |
2014-12-08T15:05:51Z |
THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:50Z |
NOVEL DYNAMIC CMOS LOGIC FREE FROM PROBLEMS OF CHARGE SHARING AND CLOCK SKEW
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:49Z |
AN IMPROVED PROPAGATION-DELAY-TIME FORMULA FOR THE SUB-MICRON N-MOS INVERTER
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WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
A NEW TWIN-WELL CMOS PROCESS USING NITRIDIZED-OXIDE-LOCOS (NOLOCOS) ISOLATION TECHNOLOGY
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TSAI, HH; YU, CL; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS
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WU, CY; HWANG, JS |
| 國立交通大學 |
2014-12-08T15:05:48Z |
CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:45Z |
ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:45Z |
A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC
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WU, CY; LIN, YT |
| 國立交通大學 |
2014-12-08T15:05:40Z |
REALIZATIONS OF IIR FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE
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YU, TC; WU, CY; CHANG, SS |
Showing items 321-345 of 607 (25 Page(s) Totally)
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