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"wu cy"
Showing items 331-380 of 607 (13 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:05:57Z |
A NEW EXPERIMENTAL-METHOD TO DETERMINE THE SATURATION VOLTAGE OF A SMALL-GEOMETRY MOSFET
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JANG, WY; WU, CY; WU, HJ |
| 國立交通大學 |
2014-12-08T15:05:57Z |
A NEW LATERAL GROWTH FREE FORMATION TECHNIQUE FOR TITANIUM SILICIDE USING THE SI/W/TI TRILAYER STRUCTURE
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LIN, MZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:56Z |
LOW-POWER DYNAMIC TERNARY LOGIC
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:55Z |
COBALT SILICIDE INTERCONNECTION FROM A SI/W/CO TRILAYER STRUCTURE
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LIN, MZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:53Z |
NEW MONOLITHIC SWITCHED-CAPACITOR DIFFERENTIATORS WITH GOOD NOISE REJECTION
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WU, CY; YU, TC; CHANG, SS |
| 國立交通大學 |
2014-12-08T15:05:51Z |
THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:50Z |
NOVEL DYNAMIC CMOS LOGIC FREE FROM PROBLEMS OF CHARGE SHARING AND CLOCK SKEW
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:49Z |
AN IMPROVED PROPAGATION-DELAY-TIME FORMULA FOR THE SUB-MICRON N-MOS INVERTER
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WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
A NEW TWIN-WELL CMOS PROCESS USING NITRIDIZED-OXIDE-LOCOS (NOLOCOS) ISOLATION TECHNOLOGY
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TSAI, HH; YU, CL; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:48Z |
PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS
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WU, CY; HWANG, JS |
| 國立交通大學 |
2014-12-08T15:05:48Z |
CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS
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WANG, JS; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:05:45Z |
ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES
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YANG, YH; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:45Z |
A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC
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WU, CY; LIN, YT |
| 國立交通大學 |
2014-12-08T15:05:40Z |
REALIZATIONS OF IIR FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE
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YU, TC; WU, CY; CHANG, SS |
| 國立交通大學 |
2014-12-08T15:05:39Z |
A NEW ALGORITHM FOR STEADY-STATE 2-D NUMERICAL-SIMULATION OF MOSFETS
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PERNG, RK; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:37Z |
THE SIGNAL DELAY IN INTERCONNECTION LINES CONSIDERING THE EFFECTS OF SMALL-GEOMETRY CMOS INVERTERS
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SHIAU, MC; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:37Z |
A QUASI-2-DIMENSIONAL ANALYTICAL MODEL FOR THE TURN-ON CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORS
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LIN, PS; GUO, JY; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:37Z |
THE EFFECT OF GATE ELECTRODES USING TUNGSTEN SILICIDES AND OR POLYSILICON ON THE DIELECTRIC CHARACTERISTICS OF VERY THIN OXIDES
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CHENG, HC; CHAO, CY; SU, WD; CHANG, SW; LEE, MK; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:35Z |
MOS DEVICE PARAMETER OPTIMIZATION BASED ON TRANSIENT TRAJECTORY CONSIDERATIONS
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WU, CY; JANG, WY; LIU, ID |
| 國立交通大學 |
2014-12-08T15:05:32Z |
AN ANALYTIC SATURATION MODEL FOR DRAIN AND SUBSTRATE CURRENTS OF CONVENTIONAL AND LDD MOSFETS
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HUANG, GS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:32Z |
EXCELLENT THERMAL-STABILITY OF COBALT ALUMINUM-ALLOY SCHOTTKY CONTACTS ON GAAS SUBSTRATES
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CHENG, HC; WU, CY; SHY, JJ |
| 國立交通大學 |
2014-12-08T15:05:30Z |
EFFICIENT PHYSICAL TIMING MODELS FOR CMOS AND-OR-INVERTER AND OR-AND-INVERTER GATES AND THEIR APPLICATIONS
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WU, CY; SHIAU, MC |
| 國立交通大學 |
2014-12-08T15:05:27Z |
REALIZATIONS OF IIR/FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE
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YU, TC; WU, CY; CHANG, SC |
| 國立交通大學 |
2014-12-08T15:05:27Z |
DELAY MODELS AND SPEED IMPROVEMENT TECHNIQUES FOR RC TREE INTERCONNECTIONS AMONG SMALL-GEOMETRY CMOS INVERTERS
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WU, CY; SHIAU, MC |
| 國立交通大學 |
2014-12-08T15:05:25Z |
PHYSICAL TIMING MODELS AND DESIGN METHODOLOGY OF BIPOLAR NONTHRESHOLD LOGIC-CIRCUITS
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WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:17Z |
NEW PHYSICAL TIMING MODELS OF BIPOLAR NONSATURATION LOGIC USING CURRENT DOMAIN ANALYSIS TECHNIQUE
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WU, CY; WU, TS |
| 國立交通大學 |
2014-12-08T15:05:15Z |
EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS
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HWANG, JS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:14Z |
A NEW METHODOLOGY FOR DEVELOPING A FAST 2-DIMENSIONAL MOSFET DEVICE SIMULATOR
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PERNG, RK; LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:13Z |
A NEW SIMPLIFIED 2-DIMENSIONAL MODEL FOR THE THRESHOLD VOLTAGE OF MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE
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LIN, PS; WU, CY |
| 國立交通大學 |
2014-12-08T15:05:10Z |
LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI
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WU, CY; CHENG, KH |
| 國立交通大學 |
2014-12-08T15:05:08Z |
DESIGN TECHNIQUES FOR HIGH-FREQUENCY CMOS SWITCHED-CAPACITOR FILTERS USING NON-OP-AMP-BASED UNITY-GAIN AMPLIFIERS
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WU, CY; LU, PH; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:04:59Z |
A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
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WU, CY; KER, MD; LEE, CY; KO, J |
| 國立交通大學 |
2014-12-08T15:04:54Z |
PHYSICAL MODEL FOR CHARACTERIZING AND SIMULATING A FLOTOX EEPROM DEVICE
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WU, CY; CHEN, CF |
| 國立交通大學 |
2014-12-08T15:04:49Z |
THE PROCESS WINDOW OF A-SI/TI BILAYER METALLIZATION FOR AN OXIDATION-RESISTANT AND SELF-ALIGNED TISI2 PROCESS
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LOU, YS; WU, CY; CHENG, HC |
| 國立交通大學 |
2014-12-08T15:04:49Z |
A NEW 2-DIMENSIONAL MODEL FOR THE POTENTIAL DISTRIBUTION OF SHORT GATE-LENGTH MESFETS AND ITS APPLICATIONS
|
CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:48Z |
HIGH-PRECISION CURVATURE-COMPENSATED CMOS BAND-GAP VOLTAGE AND CURRENT REFERENCES
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WU, CY; CHIN, SY |
| 國立交通大學 |
2014-12-08T15:04:48Z |
NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONS
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HWANG, JS; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:43Z |
A NEW METHODOLOGY FOR 2-DIMENSIONAL NUMERICAL-SIMULATION OF SEMICONDUCTOR-DEVICES
|
CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:41Z |
ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGIC
|
WU, CY; CHENG, KH; WANG, JS |
| 國立交通大學 |
2014-12-08T15:04:41Z |
A NEW OXIDATION-RESISTANT COSI2 PROCESS FOR SELF-ALIGNED SILICIDATION (SALICIDE) TECHNOLOGY
|
LOU, YS; WU, CY; CHENG, HC |
| 國立交通大學 |
2014-12-08T15:04:34Z |
A NEW IV MODEL FOR SHORT GATE-LENGTH MESFETS
|
CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:25Z |
DESIGN AND APPLICATION OF PIPELINED DYNAMIC CMOS TERNARY LOGIC AND SIMPLE TERNARY DIFFERENTIAL LOGIC
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WU, CY; HUANG, HY |
| 國立交通大學 |
2014-12-08T15:04:23Z |
A NEW GRID-GENERATION METHOD FOR 2-D SIMULATION OF DEVICES WITH NONPLANAR SEMICONDUCTOR SURFACE
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CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:22Z |
A NEW 2D ANALYTIC THRESHOLD-VOLTAGE MODEL FOR FULLY DEPLETED SHORT-CHANNEL SOI MOSFETS
|
GUO, JY; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:22Z |
THE DESIGN OF FULLY DIFFERENTIAL CMOS OPERATIONAL-AMPLIFIERS WITHOUT EXTRA COMMON-MODE FEEDBACK-CIRCUITS
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LU, PH; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:04:20Z |
A NOVEL PHL-EMITTER BIPOLAR-TRANSISTOR - FABRICATION AND CHARACTERIZATION
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CHANG, KZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:12Z |
NOVEL CHARACTERISTICS OF THE POLYSILICON HIGH-LOW-EMITTER (PHL-EMITTER) BIPOLAR-TRANSISTOR HIGH-CURRENT GAIN AND ZERO ACTIVATION-ENERGY
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CHANG, KZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:11Z |
CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:09Z |
TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION
|
KER, MD; WU, CY |
Showing items 331-380 of 607 (13 Page(s) Totally)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
View [10|25|50] records per page
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