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"wu i wei"的相關文件
顯示項目 1-11 / 11 (共1頁)
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| 臺大學術典藏 |
2020-05-04T08:08:41Z |
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor.
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Wang, Jyh-Shian;Wu, I-Wei;Chen, Yu-Sheng;Shann, Jean Jyh-Jiun;Hsu, Wei-Chung; Wang, Jyh-Shian; Wu, I-Wei; Chen, Yu-Sheng; Shann, Jean Jyh-Jiun; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 國立交通大學 |
2018-08-21T05:56:54Z |
Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture
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Liu, I-Chun; Wu, I-Wei; Shann, Jean Jyh-Jiun |
| 國立交通大學 |
2015-12-02T02:59:19Z |
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors
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Wu, I-Wei; Shann, Jean Jyh-Jiun; Chung, Chung-Ping |
| 國立交通大學 |
2015-07-21T11:20:38Z |
Extended Instruction Exploration for Multiple-Issue Architectures
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Wu, I-Wei; Shann, Jean Jyh-Jiun; Hsu, Wei-Chung; Chung, Chung-Ping |
| 國立交通大學 |
2015-07-21T08:30:56Z |
Dynamic Memory Optimization and Parallelism Management for OpenCL
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Hsu, Chao-Hung; Wu, I-Wei; Shann, Jean Jyh-Jiun |
| 國立交通大學 |
2014-12-12T02:44:03Z |
特殊應用計算加速器設計之研究
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吳奕緯; Wu, I-Wei; 單智君; 鍾崇斌; Shann, Jyh-Jiun; Chung, Chung-Ping |
| 國立交通大學 |
2014-12-08T15:46:56Z |
Instruction set extension exploration in multiple-issue architecture
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Wu, I-Wei; Chen, Zhi-Yuan; Shann, Jyh-Jiun; Chung, Chung-Ping |
| 國立交通大學 |
2014-12-08T15:46:46Z |
ETAHM: An energy-aware task allocation algorithm for heterogeneous multiprocessor
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Chang, Po-Chun; Wu, I-Wei; Shann, Jyh-Jiun; Chung, Chung-Ping |
| 國立交通大學 |
2014-12-08T15:35:40Z |
Improving Performance of JNA by Using LLVM JIT Compiler
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Tsai, Yu-Hsin; Wu, I-Wei; Liu, I-Chun; Shann, Jean Jyh-Jiun |
| 國立交通大學 |
2014-12-08T15:27:06Z |
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration
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Wu, I-Wei; Chung, Chung-Ping; Shann, Jean Jyh-Jiun |
| 國立交通大學 |
2014-12-08T15:10:55Z |
Instruction set extension generation with considering physical constraints
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Wu, I-Wei; Huang, Shih-Chia; Chung, Chung-Ping; Shann, Jyh-Jiun |
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