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Taiwan Academic Institutional Repository >
Browse by Author
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"wu jieh tsorng"
Showing items 81-90 of 96 (10 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:35:45Z |
A 1-V 100-dB Dynamic Range 24.4-kHz Bandwidth Delta-Sigma Modulator
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Chang, Chia-Ling; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:33:11Z |
Background Calibration of Integrator Leakage in Discrete-Time Delta-Sigma Modulators
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Wu, Su-Hao; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:31:53Z |
A 81-dB Dynamic Range 16-MHz Bandwidth Delta Sigma Modulator Using Background Calibration
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Wu, Su-Hao; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:30:05Z |
A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps
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Fang, Bing-Nan; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:29:24Z |
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
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Fang, Bing-Nan; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:28:51Z |
A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC
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Chai, Yun; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:24:43Z |
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration
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Lee, Zwei-Mei; Wang, Cheng-Yeh; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:21:05Z |
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
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Chung, Yung-Hui; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:21:00Z |
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70 dB SFDR up to 500 MHz
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Tseng, Wei-Hsin; Fan, Chi-Wei; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:20:30Z |
ADC Clock Jitter Measurement and Correction Using a Stochastic TDC
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Fan, Chi-Wei; Wu, Jieh-Tsorng |
Showing items 81-90 of 96 (10 Page(s) Totally)
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