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Institution Date Title Author
國立交通大學 2020-10-05T02:01:30Z ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience Wu, Kai-Chiang; Huang, Wei-Tao; Huang, Chiao-Yang
國立交通大學 2020-10-05T02:00:29Z Methodology of Generating Timing-Slack-Based Cell-Aware Tests Nien, Yu-Teng; Wu, Kai-Chiang; Lee, Dong-Zhen; Chen, Ying-Yen; Chen, Po-Lin; Chern, Mason; Lee, Jih-Nung; Kao, Shu-Yi; Chao, Mango Chia-Tso
國立交通大學 2020-07-01T05:21:48Z Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs Huang, Ning-Chi; Chen, Yu-Guang; Wu, Kai-Chiang
國立交通大學 2020-02-02T23:55:34Z Aging-aware Chip Health Prediction Adopting an Innovative Monitoring Strategy Wang, Yun-Ting; Wu, Kai-Chiang; Chou, Chung-Han; Chang, Shih-Chieh
國立交通大學 2019-10-05T00:09:48Z Layout-Based Dual-Cell-Aware Tests Wu, Tse-Wei; Lee, Dong-Zhen; Wu, Kai-Chiang; Huang, Yu-Hao; Chen, Ying-Yen; Chen, Po-Lin; Chern, Mason; Lee, Jih-Nung; Kao, Shu-Yi; Chao, Mango C. -T.
國立交通大學 2019-08-02T02:24:20Z Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications Huang, Ning-Chi; Chen, Szu-Ying; Wu, Kai-Chiang
國立交通大學 2019-04-02T06:04:50Z Workload-Aware Lifetime Trojan based on Statistical Aging Manipulation Tseng, Tien-Hung; Wang, Shu-Sheng; Chen, Jian-You; Wu, Kai-Chiang
國立交通大學 2019-04-02T06:04:32Z Lifetime Reliability Trojan based on Exploring Malicious Aging Tseng, Tien-Hung; Li, Shou-Chun; Wu, Kai-Chiang
國立交通大學 2018-08-21T05:56:48Z Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability Tsai, Chang-Lin; Cheng, Chao-Wei; Huang, Ning-Chi; Wu, Kai-Chiang
國立交通大學 2018-08-21T05:56:46Z Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators Lee, Kao-Chi; Wu, Kai-Chiang; Tsai, Chih-Ying; Chao, Mango Chia-Tso
國立交通大學 2018-08-21T05:56:27Z MAUI: Making Aging Useful, Intentionally Wu, Kai-Chiang; Tseng, Tien-Hung; Li, Shou-Chun
國立交通大學 2018-08-21T05:53:41Z Sensor-Based Time Speculation in the Presence of Timing Variability Chou, Chung-Han; Chang, Tsui-Yun; Wu, Kai-Chiang; Chang, Shih-Chieh
國立交通大學 2018-01-24T07:41:41Z 基於供電網竄改的製程變異感知型硬體壽命特洛伊 林淯晨; 吳凱強; Lin, Yu-Chen; Wu, Kai-Chiang
國立交通大學 2018-01-24T07:41:33Z 有效地佈署訊號轉換偵測器以實現針對老化的容忍機制 張皓淳; 吳凱強; Chang, Hao-Chun; Wu, Kai-Chiang
國立交通大學 2018-01-24T07:41:11Z 適用於正反器時序電路的時鐘樹老化容忍設計 梁詠鏗; 吳凱強; Leong, Weng-Hang; Wu, Kai-Chiang
國立交通大學 2018-01-24T07:40:38Z 基於工作週期轉換器之電路老化容忍設計 張庭瑋; 吳凱強; Chang, Ting-Wei; Wu, Kai-Chiang
國立交通大學 2018-01-24T07:39:05Z 雙時序餘裕+雙工作電壓:針對可變延遲設計的動態功耗降低 俞光隆; 吳凱強; Yu, Guang-Long; Wu, Kai-Chiang
國立交通大學 2018-01-24T07:38:52Z 基於統計性老化調配的工作負載感知型硬體壽命特洛伊 汪述聖; 吳凱強; Wang, Shu-Sheng; Wu, Kai-Chiang
國立交通大學 2018-01-24T07:38:18Z 針對可變動延遲設計時序變動之分析及最佳化 蔡長霖; 吳凱強; Tsai, Chamg-Lin; Wu, Kai-Chiang
國立交通大學 2018-01-24T07:37:01Z 實現即時的老化彈性機制藉由有效地佈署Razor Flip-Flop 黃朝陽; 吳凱強; Huang, Chiao-Yang; Wu, Kai-Chiang
國立交通大學 2016-03-28T08:17:22Z 次14奈米晶片之即時可靠度監測及壽命延長技術 吳凱強; Wu Kai-Chiang
國立交通大學 2015-07-21T11:20:26Z BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs Wu, Kai-Chiang; Lin, Ing-Chao; Wang, Yao-Te; Yang, Shuen-Shiang
國立成功大學 2014-10 BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs Wu, Kai-Chiang; Lin, Ing-Chao; Wang, Yao-Te; Yang, Shuen-Shiang
國立成功大學 2014-09 NBTI and Leakage Reduction Using ILP-Based Approach Lin, Ing-Chao; Li, Kuan-Hui; Lin, Chia-Hao; Wu, Kai-Chiang

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