|
English
|
正體中文
|
简体中文
|
總筆數 :0
|
|
造訪人次 :
51382110
線上人數 :
838
教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
|
|
|
"wu po han"的相關文件
顯示項目 36-45 / 45 (共2頁)
<< < 1 2
每頁顯示[10|25|50]項目
| 淡江大學 |
2009-11 |
Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment
|
Wu, Po-han; Rau, Jiann-chyi |
| 淡江大學 |
2009-05-24 |
Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression
|
Li, Wei-Lin; Wu, Po-Han; Rau, Jiann-Chyi |
| 淡江大學 |
2009-01 |
The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing
|
Rau, Jiann-chyi; Wu, Po-han; Liu, Chia-jung; Lin, Yi-chen |
| 淡江大學 |
2008-11 |
The Efficient TAM Design for Core-Based SOCs Testing
|
Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu |
| 國立成功大學 |
2008-09 |
Knowledge verification for fuzzy expert systems
|
Wu, Po-Han; Hwang, Gwo-Haur; Liu, Hsiang-Ming; Hwang, Gwo-Jen; Tseng, Judy C. R.; Huang, Yueh-Min |
| 淡江大學 |
2008-06 |
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu |
| 淡江大學 |
2008-06 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
|
Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing |
| 淡江大學 |
2006-12-04 |
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
|
Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han |
| 淡江大學 |
2006 |
A novel hardware architecture for low power and rapid testing of VLSI circuits
|
吳柏翰; Wu, Po-han |
| 淡江大學 |
2005-05-23 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
|
Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han |
顯示項目 36-45 / 45 (共2頁)
<< < 1 2
每頁顯示[10|25|50]項目
|
