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Showing items 41-44 of 44 (2 Page(s) Totally)
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| 淡江大學 |
2008-06 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
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Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing |
| 淡江大學 |
2006-12-04 |
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
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Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han |
| 淡江大學 |
2006 |
A novel hardware architecture for low power and rapid testing of VLSI circuits
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吳柏翰; Wu, Po-han |
| 淡江大學 |
2005-05-23 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
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Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han |
Showing items 41-44 of 44 (2 Page(s) Totally)
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