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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"wu po han"的相關文件
顯示項目 41-45 / 45 (共1頁)
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| 淡江大學 |
2008-06 |
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu |
| 淡江大學 |
2008-06 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
|
Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing |
| 淡江大學 |
2006-12-04 |
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
|
Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han |
| 淡江大學 |
2006 |
A novel hardware architecture for low power and rapid testing of VLSI circuits
|
吳柏翰; Wu, Po-han |
| 淡江大學 |
2005-05-23 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
|
Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han |
顯示項目 41-45 / 45 (共1頁)
1
每頁顯示[10|25|50]項目
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