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Taiwan Academic Institutional Repository >
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"wu tsung yi"
Showing items 21-30 of 36 (4 Page(s) Totally)
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| 大葉大學 |
2009-05-25 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
|
Wu, Tsung-Yi;Lin, How-Rern;Kao, Tzi-Wei;Huang, Shi-Yi;Li, Tai-Lun |
| 國立彰化師範大學 |
2009-05 |
A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
|
Wu, Tsung-Yi; Chen, Kuang-Yao; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 國立彰化師範大學 |
2009-05 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
|
Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 大葉大學 |
2009-04-1 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
| 大葉大學 |
2009-04-01 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
| 國立成功大學 |
2009-04 |
Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
|
Wu, Tsung-Yi; Lu, Liang-Ying |
| 國立彰化師範大學 |
2009 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
|
Lin, How-Rern; Chiu, Wei-Hao; Wu, Tsung-Yi |
| 國立彰化師範大學 |
2009 |
Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
|
Wu, Tsung-Yi ; Lu, Liang-Ying |
| 國立彰化師範大學 |
2008-12 |
Low-Leakage and Low-Power Implementation of High-Speed 65nm Logic Gates
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Wu, Tsung-Yi; Lu, Liang-Ying; Liang, Cheng-Hsun |
| 國立臺灣體育運動大學 |
2008-05-01 |
國小排球選手運動參與動機之研究
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張怡潔; 吳聰義; Chang, Yi-Chieh; Wu, Tsung-Yi |
Showing items 21-30 of 36 (4 Page(s) Totally)
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