臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T09:25:29Z	Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications	Y.-H. Chou;J.-L. Huang;X.-L. Huang; Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T09:25:29Z	Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications	Y.-H. Chou;J.-L. Huang;X.-L. Huang; Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling	X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	A self-testing and calibration method for embedded successive approximation register ADC	X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:47:21Z	A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager	X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC	X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC	X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	A Self-Testing Assisted Pipelined-ADC Calibration Technique	J.-L. Huang;X.-L. Huang;P.-Y. Kang; J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	A Self-Testing Assisted Pipelined-ADC Calibration Technique	J.-L. Huang;X.-L. Huang;P.-Y. Kang; J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing	C.-Y. Yang;X.-L. Huang;J.-L. Huang; C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing	C.-Y. Yang;X.-L. Huang;J.-L. Huang; C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input	X.-L. Huang;C.-Y. Yang;J.-L. Huang; X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input	X.-L. Huang;C.-Y. Yang;J.-L. Huang; X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input	X.-L. Huang;Y.-C. Yu;J.-L. Huang; X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input	X.-L. Huang;Y.-C. Yu;J.-L. Huang; X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A routability constrained scan chain ordering technique for test power reduction	X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG

Showing items 11-26 of 26 (2 Page(s) Totally)
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