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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:43:14Z	A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits	Shanq-Jang Ruan,; Rung-Ji Shang,; Feipei Lai,; Shyh-Jong Chen,; FEI-PEI LAI; Xian-Jun Huang,

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