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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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2019臺灣學術機構典藏
研討會
機構典藏系統RC7版本已
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Institution Date Title Author
國立中山大學 2003 An area-saving decoder structure for ROMs C.C. Wang;Y.H. Hsueh;Y.P. Chen
國立中山大學 2003 Novel complex catalyst of h 3 -(pentamethylcyclopentadienyl)dimethylaluminum/titanium(IV) butoxide (Cp*AlMe 2 /Ti(OBu) 4 ) for syndiotactic polystyrene Y.P. Chen;J.L. Hong
國立中山大學 2003 Oxidation of stereo-regular poly(styrene-co-4-methylstyrene) by cobalt(II) acetate tetrahydrate/sodium bromide catalyst Y.P. Chen;J.L. Hong
國立中山大學 2002-06 Design of an inter-plane circuit for clocked PLAs C.C. Wang;Y.H. Hsueh;Y.T. Chien;Y.P. Chen
國立中山大學 2002-05 A fast inner product processor implementation for multi-valued exponential bidirectional associative memories C.C. Wang;Y.L. Tseng;Y.P. Chen;C.J. Huang
國立中山大學 2002 Design of an inter-plane circuit for clocked PLAs C.C. Wang;Y.H. Hsueh;Y.T. Chien;Y.P. Chen
國立中山大學 2002 Bulk polymerization of styrene and 4-methylstyrene with Cp*Ti(OBu) 3 /MAO/TIBA Catalyst Y.P. Chen;J.L. Hong
國立中山大學 2001-09 An area-saving 3-dimensional decoder structure for ROMs C.C. Wang;Y.H. Hsueh;Y.P. Chen
亞洲大學 2001-01 A Theoretical Aspect of a Stochastic Sketching for Global Optimization J.T. Horng;Y.P. Chen;C.Y. Kao
國立中山大學 2000-11 Design of an inner-product processor for hardware realization of multi-valued exponential bidirectional associative memory C.C. Wang;C.J. Huang; Y.P. Chen
國立中山大學 2000-06 A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學 2000-05 Design of an inter-plane circuit for clocked PLAs C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學 2000 Design of an inner-product processor for hardware realization of multi-valued exponential bidirectional associative memory C.C. Wang;C.J. Huang;Y.P. Chen
國立中山大學 2000 A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學 1999-06 A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學 1999-05 Power-saving fast half-swing inter-plane circuit for clocked PLAs C.C. Wang;Y.T. Chien;Y.P. Chen

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